How to Perform an Averaging Function with FPGA?

[dj143]

I need to take the analog output from four load cells and scale them to Lbs units.  The four values then need to be summed for a total load.  And then I need to drive an analog output (i.e. 4-20 mA) that represents the total load.  The scaling parameters will be provided by the RT target controller and are fixed values once the system is calibrated.

The design goal is to have the analog output respond less that 5 mSec after a change to the analog inputs.  The variability (jitter?) is hoped to be less than 0.1 mSec.  In short, the analog output must be very stable and responsive to changes at the load cells.  This project will provide a reference signal to a motion control system.

The intent is to use a cRIO-9012 controller with a cRIO-9103 chassis.  Mod3 is an NI 9239 and Mod4 is a NI 9265.  We’re using LV 2009 with SP1 and Win7 for the OS.

I’m somewhat new to FPGA and am uncertain how to approach the internal code needed.  Please look at the attached code, which is my first stab at it.  The Addition function at the Total Load indicator obtains the load values from the other three load cell indicators.

I have the following questions:

Is the above mentioned design goal reasonable using FPGA?

Should I use a different chassis other than the 9103?  (I chose the 9103 because I have one.)

Is there a better or more elegant way to perform the averaging function?

What do the red (coercion?) dots mean?

Thanks,

Dave

[srm@viewpointusa.com]

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dj143 wrote:

I need to take the analog output from four load cells and scale them to Lbs units.  The four values then need to be summed for a total load.  And then I need to drive an analog output (i.e. 4-20 mA) that represents the total load.  The scaling parameters will be provided by the RT target controller and are fixed values once the system is calibrated.

The design goal is to have the analog output respond less that 5 mSec after a change to the analog inputs.  The variability (jitter?) is hoped to be less than 0.1 mSec.  In short, the analog output must be very stable and responsive to changes at the load cells.  This project will provide a reference signal to a motion control system.

The intent is to use a cRIO-9012 controller with a cRIO-9103 chassis.  Mod3 is an NI 9239 and Mod4 is a NI 9265.  We’re using LV 2009 with SP1 and Win7 for the OS.

I’m somewhat new to FPGA and am uncertain how to approach the internal code needed.  Please look at the attached code, which is my first stab at it.  The Addition function at the Total Load indicator obtains the load values from the other three load cell indicators.

I have the following questions:

Is the above mentioned design goal reasonable using FPGA?

FPGA is a fine approach to this problem

Should I use a different chassis other than the 9103?  (I chose the 9103 because I have one.)

9103 is fine for this application

Is there a better or more elegant way to perform the averaging function?

Yes, but that is not exactly the point.

What do the red (coercion?) dots mean?

coercion dots may indicate issues with the numeric representation of the calculations.  care must be taken to correctly deal with all calculations in an application like this.

Just as important is the performance.  does this compile and run?  you need to add a timing function to determine your loop rate.  you may not be making the rate you are assuming you are getting.

in general, you can replace the divides with multiplies using the inverse of the value.

you will also have to change the precedence of the additions to make them a bit more parallel instead of straight cascade.

you should be able to use this approach to your problem if it compiles and you don't have to do any other work on the FPGA.  if it does not fit, you will need to use a more "elegant" approach to the math.

Thanks,

Dave

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[dj143]

Hi Stu,

I started to compile this when I went home last night and when I came in this morning it had failed.  Apparently there is a "packing" problem and the VI requires more resources than are available.  I had previously prepared an FPGA project that is very similar to this.  However, that project only had three analog inputs whereas this one has four analog inputs.  It appears that adding the fourth set of shift registers pushed it over the edge.  Perhaps stringing 100 shift registers for each input is excessive.  So I'll continue to work with this.  Your responce is helpful to me for the sake of confidence.  In other words, it appears that the way I'm approaching how to average the analog inputs is the way to do it.

In the mean time, why are the coersion dots on the outputs of the arithmetic functions instead of the inputs, which is what I'm familiar with in normal LabVIEW programming?

It's not clear to me what is meant by changing the precedence of the additions.

Dave

[srm@viewpointusa.com]

I would not say that your approach is the way to do it, I said if it compiles and meets loop timing, it will suffice.  At this point, it does not compile and you don't know if it meets timing.

we would use  a variation of http://decibel.ni.com/content/docs/DOC-1128 which is a moving average function using memory.  The example would have to be modified to accomodate your fxp number.  the coersion dot at the output is disconcerting but with or without the dot, you have to be very careful with the data

[srm@viewpointusa.com]

Here is an example project with code that might be a good starting point for you.  I can't run it but there is a tick counter so you can see how fast the loop runs.  Good Luck

[dj143]

Hi Stu, I have been able to get your example to compile and run.  In the subvi (2^N Point Moving Average fxp 24.5.vi) there is one High Throughput Add function that I had to modify by setting the Execution Mode to Outside single-cycle Timed Loop.  I have the following questions: 

1)    Why is the High Throughput Add function used for this particular addition?

 

2)    What is the point behind the High Throughput arithmetic functions?  In other words, when should the High Throughput functions be used?

 

3)    The normal arithmetic functions have what appear as blue coercion dots.  What do these dots mean?

 4)    As a result of a design review meeting yesterday, it was decided to expand the number of analog inputs from 4 to 8, which requires the use of another NI 9239 module.  We will need to determine the total load of 8 load cells.  This further means that I cannot use my cRIO-9103 chassis because I’ll need to purchase an 8-slot version.  (More than four modules will be needed.)  There are currently four LX versions of cRIO chassis.  Can you possibly suggest the version that I’ll need?  I’ll be contacting my NI rep.  However, do you have any thoughts on this?

[srm@viewpointusa.com]

I coded the example in 8.6.  in 2009, the fixed point functions I used got converted to the high throughput functions.  there is no reason high throughput routines would be need for this app. 

High throuphput routines would be used when you are really trying to extract performance from your application.

the blue coercion dots indicate that the output of the function has been explicitly set as opposed to adapt to source.  a visual indication that you should not assume the output follows the rules of adapt to source.  I set these output types so the data type did not blow up causing downstream issues.

the choice of which chassis you need will depend on a couple of factors.  Size and future need.  you can evaluate if your application will fit on each without buying them.  If you don't know what else you will be adding to the applicaition, I use the biggest FPGA.  if you are making mutiple units, evaluation of the smallest one to do the job is appropriate.

What was the tick timer value of the application running?

I don't think you will have a problem fitting 8 channels into an application.  If you do, there is a way to use a single averaging function to produce a usable result.  it will take the same amount of memory space as 8 individual averages but will use less fabric to implement.

[dj143]

The tick value is 800 and will occasionally blip to 801.  What does this value mean?

[srm@viewpointusa.com]

800 ticks.  the base rate is 40 MHz.  40 MHz divided by loop time (800 ticks) is 50 kHz.  If it were greater than 800, it would indicate that you are not acutally processing at 50 kHz.  In the example, if you remove the shift registers after acquire and before output, the tick count will probably go up.  (worth doing as an experiment).

the average size is 2^8 or 256.  50 kHz /256 or .00512 msec for a step change to make it out of the average routine.

the average routine that I referenced before and modified for this example had a bug in it BTW, that is why it is important to put together a test case to verify the math.

[dj143]

I removed all the shift registers and the ticks count remains the same at 800.

The NI 9239 analog input module runs at 50kS/Sec/Channel.  Is this module setting the loop rate at 50KHz?