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How to build FPGA vi with multiple modules?

Hi Wenli,

 

I'm afraid we cannot help you by email unless you have a service contract. From our system it would appear that you are covered by your universities service contract.  Check with your supervisor that it is OK to contact us to start a service request. You can phone us on 01635 523545.

 

If you unable to do this, you can try uploading a screen shot of your code.  It is the code running on your real time system that I want to see.

 

Thanks

Lewis Gear CLA
LabVIEW UAV

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Hi Lewis,

 

Thanks. Here are some pictures of my code including module applications. Hope they can help some.

 

Wenli

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Hello Wenli,

 

I understand that you are working with Lewis on this project here on the forums, but since you have opened a Service Request with us, let's work on that and then we'll later update the forums for the rest of our users as well.

 

For now, let's just say that there doesn't seem to be any need for the use of interrupts from what we can see in your code or the description of your application. Getting multiple modules to work side-by-side is usually much simpler. We will therefore work towards removing the interrupts wherever possible.

 

Hope this is ok,

Kind Regards,

Michael S.
Applications Engineer
NI UK & Ireland

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Hey Wenli,

 

I've tried calling you quite a few times with no success, so I've just sent you an email with as much information as I could put together without discussing a few details with you first.

 

It might be useful to update the rest of the users though anyway:

 

Essentially, I don't believe there is actually an issue with using many interrupts, I believe it's how much information you are trying to pass with those interrupts. Your code currently raises an interrupt every time there is any information on the ports! This is simply too much for the controller to handle. The FPGA code has loops running at high speeds and sending up too many interrupt requests basically. One of your loops does have some code in another loop to only raise an interrupt when an EOS is found, and this is a lot better than what your other loops are doing. You should work towards this kind of functionality with the other loops as well, however you should remember you have a limited number of DMA FIFOs.

Also, your AI and AO do not need interrupts, you can eliminate those. Have a look at examples for AI/AO on FPGA.

Your code probably sends a lot of requests and inundates your controller, so it needs to be a bit smarter and only raise an interrupt when there is a complete message (for example).

 

I hope this helps a little,

 

Kind Regards,

Michael S.
Applications Engineer
NI UK & Ireland

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Michael,

 

I really appreciate your advices.

 

I will change my code as you said. If there is any further questions I will make a request again. Smiley Tongue

 

Wenli

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