How to use a PXIe-6569 like an NI-6585B with FlexRIO FPGA Module?

[Tedster]

For my latest project I decided to try the new (new to me at least) PXIe-6569 & TB-6569 to generate a 100MHz clock along with other user controllable LVDS outputs.

The socketed CLIP is significantly different than what I'm used to with a PXIe-7971R & NI-6585B combo.

The blocker for me is that the PXIe-6569 forces me to use a Tx Clock in my timed For Loop.  For some reason the CLIP limits the Tx Clock to 150MHz, which will result in a max 75MHz LVDS output clock I can generate.

Hacking around in the CLIP's XML I can see the max Tx Clock value is 150MHz... I'm not an expert in customizing CLIPs but would it be as easy as updating the XML to 200MHz, or do I need to make sure this change doesn't cause issues back in the original VHDL?

Or is there just a simple CLIP that already exists that is similar to using a FlexRIO board with an NI-6585B that's compatible with the PXIe-6569?

Thanks in advance for your help!

Ted

[Tedster · Accepted solution]

Was able to talk to our local Field Applications Engineer and he recommended using the SerDes clip instead of the Socketed clip.

With the SerDes clip, you can write an 8 bit value for each channel and it gets streamed out at each Tx Clock cycle. Or maybe a better way to say it is that 8 bits is streamed out each Tx Clock cycle.

So to generate a 100MHz clock output, I can write the value 0xAA and set Tx Clock for 25MHz.  The resulting output for my desired channel is a 100MHz clock (verified by measuring with a scope).

Thanks Kyle Mozdzyn for your help!