NI 9223 at 1Mhz on a cRIO-9024

[negnin]

Hi All,

I'm trying to use the 9223 module to sample at 1Mhz using User-Controlled IO Sampling.

The 9223 should be able to simultaneously sample 4 channels at 1Mhz (that's why I bought it), but I can't get it above 500khz.

I'm using the "NI 9223 User-Controlled IO Sampling" code from the LabView examples (see attached), which works fine with a sampling period of 2 uSec or above, but at 1uSec I get the attached error.

The example code has a warning saying some cRIO controllers can't keep up with 1Mhz rate of the NI 9223. I'm using a cRIO-9024, but I can't find the relevant specs on sampling at 1Mhz for it. Could this be the problem? This cRIO/module combo was recommended to me by a NI rep with one of my requirements being sampling at 1Mhz, so I hope that's not it...

Anything else I can do to get it to run at 1Mhz (or at least at 750khz)?

Thanks!

[PeanutButterOven]

Hello negnin,

I noticed that you modified the example code for the User Controlled I/O on the FPGA side. While most of it looks good, you removed the pipelining functionality that originally existed. If you open the original code you will notice that when the FPGA I/O Read method occurs in the second loop it immediately puts the data into a shift register, on the next loop the cycle the data is shifted into the fifo, once the pipeline is filled these operation happen concurrently within the loop. If you are familiar with HDL languages this would be analogous to inserting flip flops (registers) in between operations. As you have it the Read method has to occur and the array built and then inserted into the fifo, which will eat up time and effect the loop rate. With that being said, you should try to run the original examples on the FPGA and Host side to see if the 1 MHz rate is achievable, and then modify your code to have the same functionality.

[negnin]

Hi,
Thanks for the reply. I actually didn't change anything in the example code and uploaded it straight from the examples.

What code are you comparing it to? I'm running LabView 2011. Maybe it got updated?

Do you mind sharing the vis?

Thanks a lot!

[PeanutButterOven]

negrin,

Not sure if it was updated from 2011 but I attached a screen shot of the 9223 FPGA code for your reference. It will show you what I was talking about in my last post.

[negnin]

Thanks for the code!
I tried your version and at least it runs and I don't get the error anymore.
However, it now times out above 500khz. I tried timing it using ticks and it times out at 78 ticks (513khz).

This is the exact code that you posted in the screenshot.

Any ideas how to troubleshoot this?

Thanks!

[PeanutButterOven]

negin,

I will try to get the hardware and run the code myself to see if the rate is achievable. I will post back as soon as I am able.

[PeanutButterOven]

Before I requisition the HW I thought I should confirm how you are bench marking the code. Please provide images too.

[negnin]

Sorry for the late reply. I decided to install LabView 2013 since the code has obvioulsy changed between versions and I hoped it might solve my problems.
In short, the 2013 host code is also different than the 2011 example code. The 2013 code actually works at 1Mhz. However, it does not graph the data continuously. The 2011 code has the graph inside the while loop, while the 2013 code displays it after it acquired all of the samples (outside of the while loop). The number of samples that it can acquire is limited.

In my application I'll be running code on the FPGA at 1Mhz. It will control a voltage output based on input idependent of the host. However, I also need a continuous display of the data on the host and the ability to data log a couple of seconds at a time at the press of a button. This host code is all working, but times out at the 1Mhz that is required to run the FPGA code.

What I am now considering is putting two versions of the FIFO code on the FPGA. One running in a different loop that runs slower that is used to display the data continously and another one that runs at 1Mhz for data logging that will only gets called occasionally and does not need to be continuous.

I'm not completely happy with that solution however, because I'm used to pausing the graph at will to inspect the data and it will mean rewriting of some code.

I've attached the 2013 FPGA example code and 2011 Host example code. Ideally these would work together at 1Mhz (right now it times out at 76 ticks). Any ideas how to get this to work would be greatly appreciated!

Thanks in advance!

[PeanutButterOven]

negnin,

The best bet would be to create another thread to handle the processing time of displaying the data continuously. Once the HOST code reads the data off the FIFO put it into a queue and then de-queue the elements in a parallel While Loop and display them there. This will let the Host's FIFO read as fast as it can and for you to view the data in real time.

[negnin]

Hi PeanutButterOven,

Could you expand a bit on this, or show me an example of what that would look like?

I'm unsure what you mean with putting the FIFO data in a queue.

The idea makes sense though, so I'd like to try it.
Thanks!