Question about Fixed Point (FXP) data type and DMA Reference Triggering in LV FPGA 8.6

[VLg]

Hi there,

I am using LabVIEW FPGA 8.6. Hope you guys can help me out with this. 🙂

The first qn is related to the Fixed Point (FXP) data type. If I have such a data type with 16 bits word length and 4 bits integer word length, does this mean that on the FPGA this is represented by 20bits total? E.g. if I have 64 bits of memory on the FPGA, does this mean I can store 3 FXP data in this memory? Or is it that 32bits is needed to store a 20bit FXP (e.g. is there such a thing that the memory is divided into 32bit blocks, so even if the data is less than 32bits, only 1 data can be stored in a block?)

The reason for this question is that I am implementing a triggered acquisition for multiple channels, getting pre- and post-trigger samples for each channel. I am using the example program "DMA Referenced Triggered Acq - cRIO" (found at "\LabVIEW 8.6\examples\CompactRIO\FPGA Fundamentals\Dma"). For this example a local FIFO and DMA FIFO are used, but of small sizes (~2k). To get 2k of post and pretrigger samples, a 2k DMA and local FIFO is required.

The issue is that my application requires a long post-trigger time (about 5-10s), and at a sampling rate of 10kS/s and above. Going by the same concept as the example program, I will need a 100k FIFO to get 10s of posttrigger samples for a channel sampling at 10kS/s, which is way past the memory limit of most (if not all?) FPGA chassis... Because of this constraint I also cannot expand it to 4 channels.

If anyone has a better idea of how to implement this, I will be glad to hear you out! 🙂

Thanks in advance and merry xmas!

Best regards, 

VL 

[KateB]

Hi VL,

I know other guys face the same problem, but he uses USB-9239 instead of cRIO.

With this such a long pre-trigger, I don't think keeping all pre-trigger data on FPGA is a good idea.

I'd suggest to transfer data to a controller and keep them in array.

Then, you can manipulating and array to keep pre-trigger data until trigger is armed.

Regards, Kate

[MehakD]

Vlg,

I am sorry that you had to wait this long to get a reply to your post. Somehow the e-mail notification for this post didnt seem to make it to our support e-mail box and was thus not assigned out correctly.

As for your questions, I am providing the answers in order:

1. For a FxP the word length is the total precision of the number, including the integer and the decimal part. So for example in your case if you have 16 bit word length and an integer word length of 4 bits, then the total precision of your number will be 16 bits with 4 bits allocated to the integer part of the number and 12 bits allocated to the decimal part of the number.

2. The memory on your host side of the FIFO will always be accessed in packs of 64 bits for each FxP number. However on the FPGA this may vary for every block of memory. Depending on your target memory can be configured for different port lengths and depth. For example if your target(example Virtex II Pro) supported memory in chunks of 18 KB then the follwing configurations can be used for the Memory Blocks :

16 K X 1 bit, 4K x 4 bit, 1K x 18 bits, 8K x 2 bits, 2K x 9 bits, 512 x 36 bits (the Xilinx datasheet for Vitex II pro contains this information)

So depending on the precision of the data, memory will be configured accordingly and difference in port widths may result in the presence of some unused bits.

3. What target are you using? Depending on the FPGA chip on your target you could have different Memory sizes. You can refer to their specs to find out more information on how much memory you have. For example Virtex II 1000 chips have 82 KB of RAM whereas the Virtex II 3000 chips have 192 KB of RAM. Also if you do run out of RAM then you have the option of storing the data on the FPGA fabric as flip flops or LUTs.

I hope this helps in answering some of your questions.

Regards

Mehak Dinesh

Applications Engineer 

National Instruments