RT 8.6.1, PCI-6259 and Timed Loops

[Rick_F_Foster]

I just upgraded my system from 8.5 to 8.6.1 and am having a problem getting a timed loop executing again as well as it did in 8.5.

I am simulataneously running the AI and DO functions on the PCI-6259 mouted in a PC running RT 8.6.1. It is acquiring pixel data from a detector (AI), and generating the control signals to the detector (DO).

Under RT 8.5 I acquired 66,560 pixels at 312,500Hz, which takes 213ms. I set the timed loop to execute every 263m (The system seemed to need >20ms to set itself up for the next frame).

When I installed RT 8.6.1, I am not getting anywhere near that performance. It seems like I need on order of >500ms between iterations and I can only do that well by manually setting the timeout to the "Wait Until Task is Done" on both the AI and DO tasks to some number closer to my acquisition time.

When I run just the AI task in the timed loop, things seem somewhat sane. IT is when I run the DO concurrently that things seem to go south.

On the DO side, I am using the AI Convert exported to PFI15 as the clock source for the DO (after each sample, I have the DO set the next pixels controls and addresses). The DO is outputting a U32 on P0. As I said, it kind of works, except it seems like it takes a long time to get set up and I end up dropping iterations (The loop is in DM mode).

I have been scouring the web and found it a bit confusing on what the proper way to set up a DO inside a RT Timed loop and when to start/stop it (inside or outside the loop).

Any hints or examples would be appreciated. In particular something that is recommended for initializing and executing DO in an 8.6.1 RT loop.

Rick

PS: The U32 data that is being output on P0 is larger then the PCI-6259 onboard buffer, so I think the RT system must be using DMA to transfer the data to the onboard buffer as it needed it (there are 66,560 U32 values that are being output to P0 during each timed loop period).

[Peñata]

Hi Rick,

I have a few things I would like you to try:

1.) Right-click the border of the timed loop and select Replace with While Loop and then right-click again and select Replace with Timed Loop.

2.) Right-click the border of the timed loop and select Remove Timed Loop and then drop down a new Timed Loop.

3.) Open a new VI and copy/paste your code to this new VI.

Thank you for choosing National Instruments.

Aaron Pena

National Instruments

Applications Engineer

http://www.ni.com/support 

[Rick_F_Foster]

Yes, I tried that earlier, along with mass recompile.

But I still seem to be always dropping a frame before PCI-6259 is set for the next aquisition (The Timed Loop is in Discard and Maintain Phase mode).

This is not a real big deal for my current application, but will be a problem for my next experiment. Something in 8.6.1 seems to be taking longer to set up the PCI-6259 for the next acquisition/DIO or the wait til done function is taking longer to realize the acquisition/DO is finished.

Performance seems to be pretty good when I only run the ADC task, it feels like the holdup is the wait til done figuring out that the DO generation is complete, which causes it to drop a frame. So my gut feel is there is something in the wait til done that takes too long to figure out the digital out pattern generation has completed. But that is just a feelin.

Rick

[Peñata]

Rick,

Have you been able to reproduce this issue on a smaller scale? Can you write a new VI that exhibits this same behavior? If so, please do so and post it.

Thank you for choosing National Instruments.

Aaron Pena

National Instruments

Applications Engineer

http://www.ni.com/support

[Rick_F_Foster]

I have not tried to write another program yet.

But scouring the forum and web, I seem to think that some version of LV's "wait until done.vi" may be polling based. Can you comment on how wait until done is actually implemented and if it is polling based, can the poll be set to a smaller period?

Thanks

Rick

[Peñata]

Hi Rick,

Yes, I do believe the DAQmx Wait Until Done VI is polling based and it is a blocking VI. As far as setting the poll to be a shorter period, I doubt that is possible.

Thank you for choosing National Instruments.

Aaron Pena

National Instruments

Applications Engineer

http://www.ni.com/support