Thanks all for the great advice. I was a little slow catching on to cores versus CPUs as sometime these terms are used a little interchangeably - meaning sometimes CPU is referring to a sperate core within a physical CPU.
I expanded the application out to have two timed-loops.
I also added some load-balancing with the RT SMP CPU Utilities vi set and assign pools VI to give
CPU_0 OS tasks I use this to run the house keeping of the application
CPU_1,2 Timed Loop for the heavy lifting Time_Loop_1, the Time Loop is configure to use any CPU ie -2
CPU_3. is set in the Time_Loop_2 for the lighter lifting Time Loop for reading USB and FPGA controls.
I am not sure if this was the best way to make the allocation.
I also added Start timed loop synchronization. To always have both loops start simultaneously as they are set to have the same loop time.
Using the RT Get CPU Loads I have
~ 50% on CPU_0
~ 35%/50% on CPU_1,2.
Timed_Loop_1 now completes in 80% of allowed time at max load down from 95%
~ 25-30% on CPU_3
There is some loop to loop timing jitter but well within the determinism needed.
So all is good. I may still have to make some modifications that is to have Timed_Loop_2 wait for Time_Loop_1 to complete some 70% of its tasks, before TIme_Loop_2 reads some data to then feedback to Time_Loop_1. This should be OK as Time_Loop_2 does not have that high a load and can complete in the its loop time. Still I hope I can avoid this as it will take a bit of juggling to make sure Time_Loop_1 has most of the time the time relevant data. I most use Functional Globals to pass data around the application, but perhaps it is time in this case to explore 'channels'
