Setting Sample Rate NI 5762

[jarrisonwins]

We have a NI 7966R FPGA with a NI 5762 digitizer. Is it possible to configure the sample rate of this digitizer so that we are not running at 250 MHz? Ideally we would like to sample at 10 MHz.

[Haagen-Dazs]

Hey Jarrisonwins,

I have linked the manual below that shows the accepted range for CLK IN values for the 5762. You will notice that the low end of the range on page 9 is 150 MHz. What this means is that we cannot configure the 5762 to run that slow but we can ignore samples that are being read in. If we have the 250 MHz clock then we can setup a counter in our FPGA code that only uses a sample read every 25 iterations. This should divide the sampling rate down to 10 MHz and give you the functionality that you are looking for.

 5762 Manual:

http://www.ni.com/pdf/manuals/375651a.pdf