Sliding mathematic functions in FPGA

[sesexton]

Hello All

I am evaluating the FPGA module in conjunction with the sbRIO product, and I was wondering if there existed any functions that allowed for sliding time window RMS measurements. The canned RMS function accepts one value at a time, up to the specified # of samples, then calculates and outputs the value. It then clears all of the stored values and begins collecting new data. So we end up with one RMS calculation every n samples, rather than a moving window measurement, with continuous output after n samples, similar to the Pt by Pt functions in the base package. It's easy enough to add a for loop and create an array with depth n where we queue the data through, but it seems an inefficient way to accomplish this measurement. I would appreciate any ideas.

Thank You

Sean Sexton 

[srm@viewpointusa.com]

I do not know of a public version of RMS as you describe.  However, instead of using an array to store previous values for the sliding windows, use memory.

[Hueter]

Sean, I agree with Stu that you can use array functions to make a windo for your RMS data. I created a quick example that allows you to use a slider on the front panel to select a window of data.

 

[srm@viewpointusa.com]

the question was using the FPGA RMS function.  My reply was to focus on using FPGA memory as opposed to a LabVIEW array construct in re-working the function.

[memoryleak]

Sean,

     If I understand you correctly, you might be able to accomplish your goal by creating a circular buffer and calculating the RMS value after each sample (or X samples, depending on your throughput capabilities) using the contents of the circular buffer.  If you choose your window size to be a power of two, the circular buffer could be done very very efficiently.

     This, however, requires you to be able to write 1 samples and read W samples (size of window) out of memory every time you get a new sample.  This may not be possible, depending on how fast your sample rate is and how big your window is (Ex: a 256 point window at 40Ms/s probably wouldn't be possible using this method, unless labview does something terribly awesome with it's memory creation).

     If you really have the need for speed, you could always create W individual registers (assuming W is small) and keep a running sum of the squared incoming samples, but I wont bother with that because it's likely that your FPGA is running much faster than your sample clock 🙂

Hugs,

memoryleak 

P.S.  power-of-two sized circular buffers are incredibly useful in FPGAs... bonus points if you write a good one and want to post it for others to use!

Message Edited by memoryleak on 09-18-2009 04:51 PM

[sesexton]

Thanks for the help everyone!

Memoryleak : I am only sampling two input channels at 1KHz, with my circular buffers being 100 samples deep. So my aggregate data rate would be in the 200KHz range. 

Sean Sexton 

[srm@viewpointusa.com]

observe the algorithm closely and you realize that you don't need to process the entire array each iteration.  just keep track of the sum of squares and subtract the earliest point squared and add the newest point squared each iteration.

Much more efficient.

Not sure what you mean about the circ buff.  We use FPGA memory to implement the circular buffer.  power of two size is not important.