Timing issue with cRIO FPGA mode.

[adamstong]

We have a function generator sending a 10Hz 0-10Vp-p signal to a NI 9215 docked in a cRIO running in FPGA mode. The VI is set to sample the input at 1khz (1ms interval) for 1000 points. So I was expecting that it should take exactly 1 second to complete with 10 cycles of sine wave when the data is plotted.However, what we ended up with is that it captured more than 10 cycles in 1000 data points. And that the elapsed time took about 1.12 second to complete.  Can someone explain why I am seeing this result? I don't think 1khz is a high sampling rate that would slow down the cRIO for capturing the data.

If we use the Simulate Sig block to simulate an input instead of a real physical, input, then it would be fine.

 

 

[Terry_ALE]

You must use a DMA-FIFO for the FPGA to RT transfer https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgaconcepts/fpga_dma_how_it_works/

The function you are using is for setting static values such as settings.

[adamstong]

@Terry_ALE Thank you fro your reply. I haven't accepted your respond as a solution because I ran into a differemnt problem with LabVIEW. Thus haven't had the chance to try it. Hopefully, I can get the cRIO up and running again soon.