Using both CAN Channels on cRIO with 9853

[jct5016]

I have a 9014 cRIO RT Controller and 9112 Chassis and a 9853 CAN Module.  I successfully used the example projects CAN Channel Recieve and CAN Channel Transmit to verify the hardware works.  Then I took both FPGA VIs from each project, and combined them into one FPGA VI by merely copying them both into the same VI.  I can successfully transmit and receive with the host VIs. 

My goal now is to be able to use both CAN Channels on the 9853 module for transmitting and receiving CAN Messages on each channel.  I wish to use this in a Hybrid Mode project later, so I think there is only one available DMA Channel after Scan Engine takes 2.  This might be why I get errors when I just make a copy of everything in the FPGA VI, make a new FIFO, and make renamed copies of the Host VIs with different variable names to match the copied FPGA VI Contents.

Any other Ideas on how to do this would be appreciated.

Also, I am aware CAN1 needs external power, so thats not an issue either.

Thanks,

John

[Hueter]

Could you post the code you have modified or at least a screenshot for reference?

[jct5016]

My most recent attempt does allow 2 way communication on both Channels, but the receive channels are slow and do not work if you send messages more often than say a few seconds.

I've traced it back to my FPGA VI, here it is (It is essentially a combination of the examples CAN Channel Receive(FPGA).VI and CAN Channel Transmit(FPGA).VI pasted together and copied for each CAN Channel on the 9853 module.

A field engineer told me to combine all of the FPGA Receive and Transmit example VIs in to one FPGA VI, but I didn't ask why at the time.

John

[jct5016]

Here is the VI file in case you want to directly modify it.

Thinking about it more, the reason he said they had to be in the same VI probably has to do with only one DMA channel available to communicate with the FPGA via RT Host VIs (2 of the 3 total are taken by Scan Engine is my understanding).

John

Message Edited by jct5016 on 12-11-2009 08:13 AM

[jct5016 · Accepted solution]

I figured it out, I'm not sure why, but putting some of the parts from the "CAN Channel Receive FPGA" portion in their own loops fixed it.  Now the CAN Recieve is as fast as can be, never dropping frames or overflowing the FIFO.  It also compiled the FPGA Bitfile about 30% faster and had about 50% less device utilization.  Odd...

If you are curious, heres the new VI:

 

John