08-19-2005 10:09 AM
08-22-2005 08:36 AM
If you are seeing a Timed Loop option for using the 1 MHz clock, you must not be targeted to cRIO FPGA backplane. When LabVIEW is targeted to the FPGA, your loop options include the For Loop, While Loop, and Single Cycle Timed Loop (SCTL). You will not be able to acquire from the 9233 within the SCTL because analog input cannot complete within a single tick of the 40 MHz FPGA timebase. The While Loop would be your best design option in this case.
First, target LabVIEW to the cRIO FPGA backplane (look for the VISA address in your execution target list). In your while loop, place a sequence structure. In the first frame, place a Loop Timer.vi to provide your 100 microsecond timing. Then in the second frame, place the Analog Input node for the 9233 and simply send the data to a front panel indicator at first. Add the stop button to your while loop. Finally, place another instance of the Loop Time (configured in the same way) outside of the while loop and ensure that this Loop Timer will execute before the while loop begins. You should be able to compile this VI and run the VI at 10 kHz, as you have configured.
You may also want to reference the shipping examples for the 9233, which contains an example of using the calibration data to properly interpret your input values. These examples can be found at C:\Program Files\National Instruments\LabVIEW 7.1\examples\FPGA\CompactRIO\cRIO-9233
I hope this helps.
Regards,
Kristi H
National Instruments