Xilinx Compiler stucks in Idle mode when I implemented a sine generator in my VI

[Patrick Röth]

Hello,

I've got a simple VI (FPGA target on sbRIO) with a sine generator, when I start the VI the Xilinx compiler opens and do something. After a few seconds the compiler goes in idle mode and stucks there. Here a schreen shot of the compiler window:

When I delete the sine generator in my VI the compiler works correctly and generate the bitstream.

Any ideas what's wrong?

Best regards

Patrick Röth

[noli]

Hi,

  Would it be possible to post your project with the offending vi?

[DianaS]

Hi

what happens if you try to compile a shipped Example from Labview Example Finder?

[Patrick Röth]

Hello,

I've find the problem by myself!

I remembered that I must start the Xilinx compile server once with administration privileges for complete activation.

Normally I've no administration privileges.

Problem was the "Root build directory" in the configuration of the compile server (the default value for this setting is "C:\NIFPGA86" under LabView 8.6.1) within this directory I've just limited read/write privilegs so that I've changed this "Root build directory" (see picture) to a directory with full read/write privileges and than it works!

After this I've changed in the configurations of the "Compile Client" (see "FPGA Module Options" of the projekt) the "Client Working Directory" to the directory seeing in the next picture:

After this the compiler works and generates the bitstream file successfully!

Thanks for help!

Best regards Patrick Röth