Hi,
Thank you for your reply. I have already installed the Labview FPGA Xilinx 10.1 and 10.4 on my computer. I can compile without any problem a regular vi on FPGA using Xilinx ISE. The error apears once I try to add a Xilinx Coregen IP block in my vi. I choose a square root function block because it needs minimum configuration. It seems that is a GCC compile error as it is mentioned in the following link.
http://www.xilinx.com/support/answers/33845.htm
But I didn't undrestand how can I perform necessary changes in GCC system environement as it is mentionned.
if you need the compelet compile result :
C:\Users\213201\Desktop\XilinxCoregenIPTest>set temp=C:\NIFPGA\iptemp\xipin00C6C22E48A30E207CCDDD9C921FD32C
C:\Users\213201\Desktop\XilinxCoregenIPTest>set tmp=C:\NIFPGA\iptemp\xipin00C6C22E48A30E207CCDDD9C921FD32C
C:\Users\213201\Desktop\XilinxCoregenIPTest>CD C:\NIFPGA\iptemp\xipin00C6C22E48A30E207CCDDD9C921FD32C
C:\NIFPGA\iptemp\xipin00C6C22E48A30E207CCDDD9C921FD32C>C:
C:\NIFPGA\iptemp\xipin00C6C22E48A30E207CCDDD9C921FD32C>C:\NIFPGA\programs\Xilinx12_4\ISE\bin\nt\coregen -b CORDIC_D95A0E214B830D18D0B66080503F7B0C.bat
Release 12.4 - Xilinx CORE Generator M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
All runtime messages will be recorded in
C:\NIFPGA\iptemp\xipin00C6C22E48A30E207CCDDD9C921FD32C\coregen.log
Wrote file for project 'coregen'.
Customizing IP...
Release 12.4 - Xilinx CORE Generator IP GUI Launcher M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Finished Customizing.
Generating IP...
Initializing IP model...
Finished initialising IP model.
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Partition Report
XST: Design Summary
Generating Implementation files.
Generating NGC file.
Command Line: C:\NIFPGA\programs\Xilinx12_4\ISE\bin\nt\unwrapped\ngcbuild.exe
-intstyle ise -dd ./tmp/_cg
./tmp/_cg\CORDIC_D95A0E214B830D18D0B66080503F7B0C.edn
./tmp/_cg\CORDIC_D95A0E214B830D18D0B66080503F7B0C_unobf.ngc
Executing edif2ngd -noa "tmp\_cg\CORDIC_D95A0E214B830D18D0B66080503F7B0C.edn"
"tmp\_cg\CORDIC_D95A0E214B830D18D0B66080503F7B0C.ngo"
Release 12.4 - edif2ngd M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 12.4 edif2ngd M.81d (nt)
INFO:NgdBuild - Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Writing module to "tmp/_cg/CORDIC_D95A0E214B830D18D0B66080503F7B0C.ngo"...
Reading NGO file
"C:/NIFPGA/iptemp/xipin00C6C22E48A30E207CCDDD9C921FD32C/tmp/_cg/CORDIC_D95A0E214
B830D18D0B66080503F7B0C.ngo" ...
Loading design module
"./tmp/_cg/CORDIC_D95A0E214B830D18D0B66080503F7B0C_cordic_v4_0_xst_1.ngc"...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "./tmp/_cg/CORDIC_D95A0E214B830D18D0B66080503F7B0C_unobf.ngc"
...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 1 sec
Writing NGCBUILD log file
"./tmp/_cg/CORDIC_D95A0E214B830D18D0B66080503F7B0C_unobf.blc"...
NGCBUILD done.
Release 12.4 - Obfuscator M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Start obfuscating netlist ...
Obfuscating netlist successfully!
obfuscator finished
Close database CORDIC_D95A0E214B830D18D0B66080503F7B0C_unobf ...
Finished Generation Stage.
Generating IP instantiation template...
VHDL instantiation template already present, so not regenerating.
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Creating readme './tmp/_cg\CORDIC_D95A0E214B830D18D0B66080503F7B0C_readme.txt'.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
Launching readme viewer...
Launched readme viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.
Generating simulation model for this IP...WARNING:Simulator:1010 - One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running fuse with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
Generated IP unsuccessfully. Fix the above error(s) or warning(s) and generate the IP again.
Cheers
Shahin
I
