application with two crios

[RobFrom3M]

I have an application with two cRIO/FPGA modules.   The target PC has two physical cRIOs.   My development PC is connected only to one cRIO/FPGA.  I need to test some stuff related to the cRIO with resource name RIO1.  However, the bitfile download fails with error code -63191 after succesful compile.  The problem is that target driver see only RIO0.  

How do I change the system so my cRIO is connected as RIO1?

Robert

[Robbob]

Robert,

In your project tree, do you have just one cRIO and change the IP address when you wish to target the other cRIO, or do you have both cRIO's? The default resource name for FPGA's is RIO0, and this can be changed in the project by right clicking and going to properties, but what you want to do in this situation is on the Open FPGA Reference in your RT, there is an input for Resource Name, and here you can input the RIO that is on the particular target.

Let me know if this works out, or if you are still having issues.

[RobFrom3M]

Rob

I am attaching the project tree snapshot.   My interface to cRio is starfabric interface 9052.   The destination system has two cRIO 9104.  It is heavily used for the research projects so I do not get much time on it.  

My task is to support this system by developing new functions as well as fixing the problemsd.   The Labview program is quite complex.   It is using version 8.2.  I have some urgent tasks to accomplish, moving to a higher version of Labview must wait until I am done with the urgent requests.

I have setup a developement system in my office where I develop and test some of the new features.   My testing is however limited because I do not have the machine thsi labview application is running.   I also have only one cRIO 9104 connected to my development system.   I did some extensive development for the FPGA Target cRIO1.   It compiled OK on my development system but it would not load it into the FPGA because I am asking it to load it to cRIO1 and it sees the FPGA as cRIO0.

I do not want to change the cRIO from 1 to 0 because this would give me issues when I get time on the destination system.   When I am working on a destination system, I want to deal only with the problems I cannot test on my development system.

So the question boils down to this:  How can I force load of a bitfile into the FPGA for an physical cRIO1 when I do not have physical cRIO0?

Appreciate your help

Robert Grun

[Robbob]

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