Real-Time Measurement and Control

cancel
Showing results for 
Search instead for 
Did you mean: 

cRIO 9004 Real Time Features Not Available

Hello, I'm trying to work with cRIO 9004 using LV 8.6 scan mode and I was able to see the modules I have in the chassis but not noted as "Real Time Features Not Available" and when I put one of the channel in my VI and to see if it's working I see this message (see below). I also attached other image for verification.

Here's the list of s/w installed in the cRIO-9004:

DataSocket for LV RT 4.4

LV RT 8.6

NI RIO 3.0

NI IrDA RT 1.0.2

NI SERIAL RT 3.3.2

NI VISA 4.4

NI VISA SERVER 4.4

NI WATCHDOG 3.0

 

 

 

 

 

______________
KowdTek
LabVIEW 2009

One Step At A Time, Maybe Two...
Download All
0 Kudos
Message 1 of 5
(6,031 Views)

Hi KowdTek,

I am afraid that the 9002 and the 9004, using the PharLap operating system, do not support scan mode.

It is only the later 901x series that use the VXWorks operating system that can use the scan mode.

 

See http://zone.ni.com/devzone/cda/tut/p/id/7692

 

Cheers

Stephen

0 Kudos
Message 2 of 5
(6,026 Views)
Good to know, last time I talked to NI engineer he said 9004 will work with scan mode and all I need is RT module which I already  have but I was willing to renew if it will work. So I certainly need the FPGA module to get around with this...
______________
KowdTek
LabVIEW 2009

One Step At A Time, Maybe Two...
0 Kudos
Message 3 of 5
(6,023 Views)

Hi KowdTek,

The NI Engineer should have known better.  ftp://ftp.ni.com/pub/devzone/tut/crio_software_versions.htm shows the complete requirements for the various flavours of RT.

You will need to use the FPGA I am afraid.  The Scan mode requires VXWorks OS and also at least 2M FPGA backplane.  FPGA is not too hard, especially when you use FXP mode.

Beware that the FPGA can use FXP and integer math and be careful with your coding if you use DMA transfer then you have only got U32 for the transfer and have to convert your data accordingly.  FPGA programming has become increasingly easier as LABView RT and FPGA have evolved.

 

Also remember that a loop on the FPGA is controlled by the speed of the slowest I/O module if you are using Analogue I/O within a loop.  If you are using several C-series modules it often pays to have several parallel loops, one for each type (Speed) of module.  FPGA parallel loops are true parallel loops.

 

Good Luck

Stephen

 

0 Kudos
Message 4 of 5
(6,017 Views)

Stephen,

Thank you very much for all the information..

______________
KowdTek
LabVIEW 2009

One Step At A Time, Maybe Two...
0 Kudos
Message 5 of 5
(6,013 Views)