control code and read/write

[WDD]

Hello,

A simple question. When I call FPGA vi to control my machine running, I need to read data and write to a file, with very fast frequency (at leat 20Hz). In my project, control code is in one vi while read/write in another vi (I found if they are together, the data frequency is too low, only around 7Hz). However, I need to open the same the FPGA vi twice and manipulate it in parrallel, which always gives error. I want to know what is the best way to solve the problem of FPGA control and read/write data.

Thanks.

[Andy.G]

Hey WWD,

What I would suggest you do is read the data on the FPGA, pass this via DMA FIFO to your RT system do your post processing on the RT and finally pass the data to the host which TDMS streams it to disc. Have you considered this?

[WDD]

It is the logic problem. You can see from the vi attached, control code is running in two independent WHILE loop, while reading data is running in a FOR loop on the top right. I found data read by Read 32 bit val.vi in the FOR loop is in very low freqency (just around 5 Hz)(not enough data). If I use TDMS, it will write data from here (Am I right?), so the data freqency would not be increased.

I want to know where to use Read 32 bit val.vi to read data from FIFO.

Thanks.