controling the execution rate of pid loop made on host with FPGA Target as DAQ

[NSIT New delhi]

I configured the FPGA target vi for simple data aquisition and designed a pid loop between analog input and output while in the host vi. Now I set the execution rate using 'loop timer' concept as in the help. On the host front panel I had my graph indicator and also i was making LVM file of the data. The graph was displaying the output very fast not as I set the execution rate. The data I collected looked like this

time t1 : reading1

       t1 : reading 2,3,4,5 ,.......so on in vertical fashion. So I got 10 different very close set of readings at instant t1. may 5 at instant t2, like on in a random fashion . So I was unable to see the sampling rate of my aquisition there in the collected data.

please see to it.   

[CarlaU]

Hi NSIT New delhi,

I have a few questions for you regarding your post. Can you explain a bit more how your PID loop is set up? It might even be helpful if you could post a screenshot of what your block diagram looks like. Also, what is the execution rate that you are trying to achieve? What hardware are you using? And what did you mean by when you said that you are were unable to see the sampling rate? Hopefully with this information, we will be able to figure out how to get the results that you are looking for. Have a great day!

Carla

[NSIT New delhi]

hi CarlaU

well I am using NI 7831 RIO module PXI based (labview 8.2) for my experiment. I have attached the analog input-output lines from a Process Control trainer to SCB-68 connector. I am controlling the level using PID loop which I designed on the host ( I am attaching the vi file) and I have configured the fpga vi as a simple data acquisition( i.e  a analog output and input channel in an while loop with loop delay).

You will see a sampling rate mentioned in host vi and execution of the process should be based on that rate only( I have confirmed this using normal DAQ accessory). And about how to see the sampling rate , it can be seen by collecting the output in LVM file(notepad) and observing it.

well see to it.              

[CarlaU]

Hi NSIT New delhi,

Thanks for your reply. I have been looking at your question a bit more and I have a few suggestions. Have you taken a look at the examples found in the NI Example Finder? There are two great ones that use PID loops. The examples that I am referring to are Using Discrete PID-R series.lvproj and the other one is Template Multichannel PID.lvproj. The Template Multichannel PID.lvproj demonstrates using the PID (FPGA) Express VI to perform integer-based PID control in a multichannel configuration, whereas the Using Discrete PID-R series.lvproj demonstrates using the FPGA Analysis Discrete PID to perform integer based PID. Also, what is the execution rate that you are trying to acheive? I hope those examples help clear things up!

Carla