filter implementation

[sunsun]

Hii..

I am using PCI5640R fpga card...we are implementing FM in this card.. we are giving an audio file (speech) of 8k sampling frequency.Here we have a highpass filter which has a sampling frequency of 8k.The entire samples are written to a' host to target fifo 'and in the fpga,read the samples from this fifo.After that put a highpass filter.At last the filterd samples are written to 'a target to host fifo '.The problem is the samples should read at 8k clock frequency. How can i get this? In the project window i cudnt add a derived clock...Also the derived clock freq may vary from 1MHz to 200MHz...

Pls give me solution....

[srm@viewpointusa.com]

the loop running on the fpga card should be paced at 8k.  read an element from the FIFO, filter it and write it to the other FIFO.  pretty straightforward.  The host will need to keep the host to fpga FIFO from becoming empty.

[sunsun]

Thank you for your immediate reply...Do you mean while loop or timed loop? If timed loop, how can i get 8k clock? by default it is 40MHz and i couldn't make a derived clock..

1.Actually in the host side , i 've taken data from sound card and gave it to a loop which is is running 6000 times.ie 6000 samples for1 data..So you recommended to change the loop to 8000,is it sir? then written these samples to 'host to target fifo' and then run it..In the fpga i've read the samples and pass these to a Highpass filter 1 by 1 and written to a 'target to host fifo'..The fifo is put into a while loop which runs till the time out pin of 'host to target fifo' is true...

So my question is if i change the loop rate to 8000,does it mean that working at 8k clock frequncy?(the filtering in fpga is done by taking 1 sample at a time,thats why)and that continues 8000 times ..right sir?

2.After the highpass filtering, we are doing upsampling(by a factor 5).Since there is no single block for interpolation in fpga , we manually put 4 zeroes after reading a sample from fifo.Here after we are doing modulation etc.So ,that means after highpass filtering all blocks run at 40k clock frequency.How can i get this?

Thanks in advance..Hope for an immediate reply...

[srm@viewpointusa.com]

If the host is acquiring the data at 8k, then the data will be filling the FIFO at 8k samples/sec.  In this case you would not use an FPGA timer at all and use the data coming from the FIFO to pace the FPGA while loop.  My original answer would be appropriate if you were reading the file from disk and needed to pace the data stream.  the use of a while loop with the loop timer would be fine in that case as opposed to the timed loop.

 It is possible to upsample the data on the fpga within the timeframe that you describe.  You may get some more ideas from IPNet.