generate PWM signal using three phase sinusoidal signal

[university of catania]

i am using CompactRio(9014) with C modules

i want to generate a PWM signal using three phase sinusoidal signal.

i tried few things but they didn't work.

i have generated PWM signal using some other logic. but now i want to generate it using 3 phase Sine wave as input signal.

please help me out.

[rpursley8]

You need to provide a little more detail.  What do you need the PWM signal for.  What information are you trying to capture about the 3-phase sinusoid signals?

[Aashish_M]

Hi,

As Randall had mentioned please do provide more detail. None the less please refer to IPNet - LabVIEW FPGA Functions and Example IP.
This link has some PWM examples.

[university of catania]

hi

I want to generate a PWM signal and to use this signal to feed an invertor

and later on to optimize(caculate) various parameters of the invertor.

to generate a PWM signal i want to use  3 phase  AC supply as input.( this is the regular supply obtained for from genrator-motor ).

Earlier i used the concept of shift registers and other Examples provided in example finder to generate a PWM signal but no where the input is provided by user or the input was a 3 phase ac supply

So my aim is to use sinusoidal signal as input and using some logic get PWM signal as output on CompactRIO

I thought the concept of comparing sine signal and triangular signal which will give output as PWM signal but their is no triangular wave available in LABVIEW FPGA. 

so just help me out.

regards

avinash

[Aashish_M]

Hey Avinash,

If you are looking to do PWM using multiple inputs and outputs, please look at Pulse Width Modulation Example DAQ Personality.

This is an NI.com/IPnet example. Also please refer to this example if you'd like to make adaptations.

[university of catania]

hi

i just want to generate PWM signal

I need that its duty cycle should vary automatically without user interference.(we should not vary by using host.vi but it varies itself)

something like its duty cycle vary as values of sin(x) i.e. (duty cycle should be sin18,sin 24 ,sin 30,sin 36,---    , sin 90 ,--- ,sin 180 ---, sin o)

regards

avinash

[rpursley8]

so does that mean you want 3 PWM signals?  One for each of the three phases?

[university of catania]

Randall Pursley

yes

i want three pwm signals

one for the each three phases

please tell how can i do it

if possible send me some files

waitinf for reply

regards

avinash choudhary

[rpursley8]

Attached is a simulated example of generating PWM signals.  You should also take a look at the suggested links mentioned in this thread.

[university of catania]

hi

thank you for your support.

this was the algorithm i was looking for.

but i have some more trouble( sorry...)

when i use this example as Host VI it works absolutely well.

but when i use it as FPGA VI it doesn't since the "Sine wave" function used here is not executable in FPGA and many more errors.

when i used the same logic with the sine function provided in FPGA funtion palette , i don't get desired output, since here time is Scaled to 40 MHz and i can't modify it .

sorry to say but, i could come up with this trouble.

if i place this code in HOST VI than how can I make the interface between Host VI and FPGA VI

i would anxoiusly wait for the reply

regards

Avinash Choudhary

Univeristy of Catania