10-01-2009
02:33 PM
- last edited on
05-13-2024
02:19 PM
by
Content Cleaner
Hello, I have a crio 9014 fpga with 4 modules which are being run in the slower scan mode as it makes the programming easier. Our group is now at the point where we need more speed (more than 1 program cycle a second) and we need more speed. Our project is apparenlty working, it just needs more speed. Our options as we see it.
1. get rid of the crio. We can then use the modules in it with a converter case to ethernet.
http://sine.ni.com/nips/cds/view/p/lang/en/nid/205697
Question. Will this allow us to improve speed of the program. Is the crio in scan mode the bottle neck and why?
2. Go to FPGA mode. This should in theory be much faster. But, what the sales people never said is that it takes about an hour to complile each project. Thats an awful long time to wait to find out if a mistake was made. Is there a way to do this without having to wait the hour each time. Its also very complicated to program apparently.
10-01-2009 03:09 PM
I can't answer this definitively without seeing your code, but I'd be surprised if the bottleneck was the scan mode, especially at the 1Hz rate you are talking about. Can you provide a bit more detail about what you are doing and the modules you are using? How fast do you need to go?
Sending the data over Ethernet almost certainly won't yield any speed improvements (nor does it support all modules and the driver isn't available for cRIO)
FPGA can be used to achieve faster rates than with the scan mode, but before you take this path I think we should understand exactly why you are unable to meet your performance requirements.
Thanks,
Sebastian
10-01-2009
06:11 PM
- last edited on
05-13-2024
02:21 PM
by
Content Cleaner
jimmyinCT wrote:
2. Go to FPGA mode. This should in theory be much faster. But, what the sales people never said is that it takes about an hour to complile each project. Thats an awful long time to wait to find out if a mistake was made. Is there a way to do this without having to wait the hour each time. Its also very complicated to program apparently.
You could debug the application on the development machine using Simulated I/O. Have a look at the following link:
Debugging FPGA VIs on a Development Computer (FPGA Module)
And, be sure to know the behaviors that you need to consider when doing so:
Communicating with an FPGA VI Running on a Development Computer (FPGA Interface)