07-23-2006 07:26 AM
07-24-2006 05:47 AM
07-24-2006 07:33 AM
Cheers this works fine. I had thought the VI i had before used DMA. Regarding the other post, that worked fine as well although i hope to move it more on to the host when i am more familiar with LV as i would like to make the signal far more complicated and be able to compare the outgoing signal to the incoming.
Thanks for your help
Ern
06-14-2007 07:47 AM
Hello,
I have got a question in that case. I am using a cRIO plus a 9215-Module. The controller is reading data
form the 9215 directly through the FPGA (without FIFO) every 10 ms. The problem is, that there is no change in data for
about 150 ms, so approximatly 10-15 samples have the same value. It looks like the sampling rate of
the 9215 is much to low. How can I solve this?
Thanks,
Rudi