how can i achieve desired data rate with all 3 DMA fifos.

[Pratima]

Hello,

            I have posted this query three -times in different different way.please solve my issue,I stucked here.

I am using cRIO-9004 controller(8 slot chasis,3M Gate array,512 MB flash memory),AI-9201,AI-9233(IEPE module),AI Bridge NI-9237.

I want to acquire data from all modules at maximum frequency.So i used all available fifo.Each module sends the data through FIFO.all fifo having depth 1024.i have used 3- parallel while loops for each module where data are stored in FIFO.

again I used polling method at RT side to poll data from each FIFO where i used depth 200000.at RT side i have also used 3 independet controllable while loops.

My whole program is running well without any error,but i am lossing data.i want to clear how i know that data is being lost.

In FPGA program:

Expected Data =total iterations(scans) of Data in FPGA * no. of samples which is to be written in FIFO(in every iteration)

In RT program:

Actual data=using shiftregister to addup size of FIFO array in each polling iteration.

both is not match so i analyse i am not able to achieve my desired data rate.

i think synchronisation is not required for NI-9233 and NI-9237 beacause both are being used in separate loop and storing data in fifo independtly.

[The Specialist]

Hi Pratsha,

I guess I have a few questions:
1)  How are you able to tell that your data is being lost?
2)  Are you receiving any errors?
3)  Where are you storing your data after pulling it out of the FIFO?
4)  What is the CPU load on the cRIO?

Also could you post you simple project.  By simple project I mean the RT side simple pulls data out of the FIFO, and the FPGA simple puts data into the FIFO.  Also include how exactly how you tell that you are missing data.  Have a good one.

[Pratima]

hi specialist,

                       I mean, data is being lost as i have explained in my previous post.i think that was not too much clear.Actually at FPGA side I use 3-parallel while loops.I  can set looptimer(data rate) and send data to each FIFO.Samples are sent in each iteration are #5.then i am also counting iterations of each loop in FPGA.so total number of data which should be=total no. of iterations* # of samples in each iterations(that is FPGA side).at RT side I configured all 3 fifos depth according to data rate.and i acuiring data from all the FIFO through polling mehtod.I am not storing data.but i am reading array size in each iteration and adding with shiftregister.After stopping my application out put of shiftregister will be total number of data which have been polled from fifo.Both should be same,eventhough i am first trying to acquire data at lower sampling rate (@10kHz,@1Khz).I think above explaination would be clear to you.

I am not recieving any error(no overflow ...........nothing is there).

I am trying to store my data in the RT controller but this is optional,I mean if user press the button to store then only it will store.If user does not want to store then i didnt use any indicator to read the data but i am reading data size and using shift register to add this in each iteration.

when I run my RT program.while this is being deployed it shows 57% memory is remaining out of..........

I am also surprised that I am using 512MB flash memory in my RT.but it is not showing this data while deploying.How much memory is required to run an RT application?How can i save memory for application so that i can store my data as much as possible.

If CPU usage is 100% then what is exact remedy to solve this?

Pratima

[StevenA]

Pratsha, take a look at this thread where Bassett attaches some samples of how to use interrupts in the DMA transfers, this technique may help your CPU usage.

http://forums.ni.com/ni/board/message?board.id=280&thread.id=2913&view=by_date_ascending&page=3

[The Specialist]

Hi Pratima,

The reason I asked for the code is incase your are doing something wrong that is causing a false error.  Also, since you are doing 3 DMA FIFOs and 3 while loops, do you see the problem if you only do a single FIFO and while loop?

If the CPU is 100% then the remedy is to reduce your processing.  This is done by reducing your processing speed with waits or reduced loop time.   Once agian a simplified portion of code the shows the problem might help best in what you are doing.  Also make sure that every loop has some sort of down time (wait).

[Pratima]

hi,

      After a long time,I am communicating with this thread.

 i tried with single while loop with single DMA fifo,Now CPU usage is not 100 percent.please give me some answers as my below queries:

1.can i retrieve data from all three fifo using single while loop.If i use single while loop with three fifos they should be used in parallelly or serially.

2.My Data rate is 6.4 MBps(32 channels @ 50 khz)(with single DMA fifo).How can i send my DATA deterministic way from RT to Host PC.My communication protocol is Shared variable with RT fifo and network shared variable. I stuck in configuring buffer size of RT fifo,how can i calculate the RT fifo size.

If my query is not much clear i will retry to explain in better way.

Pratima

[Jennifer_R]

Hi Pratsha,

Do you get a timeout on the FIFO write when data is lost?  One way to optimize the code is to use pipelining, reading the AI data during one iteration and writing it to the FIFO on the next iteration. 

It sounds like you are using network-published shared variables with the Real-Time FIFO enabled.  Are you using buffering?  The size will be the number of elements the buffer can hold.  More information about shared variable properties can be found here.  

[The Specialist]

Hi Pratima,

"How can i send my DATA deterministic way from RT to Host PC"

Shared variables, as well as other communication protocols can NOT send data determinitically.  This is because SVs are built upon TCP protocol which is inheritantly non-determinitic (interupt based).  Is there a reason you need determinism between the host and target?  I can't really think of a reason other than your host being part of the control loop (a bad idea).

Hope that helps.

[Pratima]

Hi Specialist,

I have done  many heat and trial for all communicatin protocol,but result is non-deterministic behaviour RT-HOst.anyway now i am doing an application using cRIO-9014 as standalone application.

             I am using cRIO as standalone application using USB mass storage device,file writing operation is in NPL loop,file writing with external device is very slow,I used RT-fifo concept.Ifwhen  i use internal storage for logging data i dont have such problem,but this problem is with this external.my mean NPL loop get slower

if i increase the size of RT fifos.but it limits the time,that means i have to decide size according to how many long i want to log data otherwise Fifo will overflow.

I want to store my data with many hours.how can i overcome this problem.

with regards

Pratima

[Kevin_S]

Hi Pratsha,

As far as transferring data deterministically, using a USB device is not the way to go since the USB communication protocol is non-deterministic itself.  Basically the only way to pass data deterministically inside the Real-Time environment is to use an RT FIFO (a global variable for instance with the RT FIFO enabled).

If you're looking at a long-term data storage method, I might recommend saving the data to the actual embedded controller itself (using an RT FIFO enabled global variable for instance).  You could then create another program that would periodically FTP into your controller on the network, copy the files off of the controller, and then delete them.  Of course, you could store data to a USB stick because you probably don't need the actual saving of the data to be deterministic, or do you?  You just need to be sure that the stick can be saved to fast enough and that it has the amount of memory needed.

I hope this helps,

Kevin S.

Applications Engineer

National Instruments