how to build a reconfigurable fpga and save the changes

[lugges]

Hi I'm using a sbRio (9632) in a small race car. (I'm trying to get it working... ;))

i want the fpga VIs to have some values that i can change trough a host vi on my computer. The Realtimecontroller has a host vi, which runs the fpga VI and initializes the values on startup. while the VI is running i would like to change the values for testing through Wlan/lan. If I found out that the new configuration was better than the old one I would like to save the changes. The RT Vi should load the changed settings at the next boot of the system.

My Idea is, to create a variable(memory) for all the configurable values on the fpga. The RT Host VI should read the values from a file which is located on the sbRIO and initialize through a special vi on the fpga the variables and closes it. then opens the fpga main vi. The VI on my Computer that i reach through WLAN/LAN uses the same fpga vi to manipulate the variables. On the frontpanel of that vi is a button that can save the changed settings to the file and create a backup from the old one.

Now my questions:

Is this working?

Are there better solutions?

Do I need this 3rd Vi on my Computer or can I manipulte the data through the RT controller?

How can I save a file on the sbRio

How can I read a file from the sbRio

I hope you can help me.

regards Lukas 

PS: you can awnwer in german if you want to 😉

[StevenA]

lugges,

lots of basic architecture questions.  Have you taken a look at the Compact RIO Developers Guide?

CompactRIO Developers Guide

Typically I like to create a data cluster with all my critical parameters on the RT target.  You make this data cluster so you can change them through direct edit on the front panel, or so the program can make changes.  This data cluster is then saved to RT disk each time you close the app, or when values change as you like.  When the RT application starts up, you read from disk these values and subsequently write them to the FPGA vi.  Because the FPGA will startup much faster than the RT vi, you may add some simple code for the FPGA to wait until valid values of you parameters are sent from the RT target.

steve

[lugges]

thanks for your help!

The cluster sounds accaptable for my project. I've been trying to create one. but I dont know how to store it at the RT controller pls help!