how to optimize compilation on FPGA

[hema]

Hello,

I have cRIO 9104 and have programmed all the 8 slots of the cRIO in the FPGA VI. i have 9215 two modules,

one 9237, 9403, 9411 modules. I have each module as separate while loops in FPGA VI. there is no timed loops in FPGA.

Also for the 8 channels of two 9215, i am calculating RMS using DC and RMS.vi inbuilt function. so i am having 8 such VIs.

i have calculations done in FPGA for the 9237 module, for the linear and rotory drive modules which involve comparison, multiplication and division. there are around 20 local variables in the FPGA. It takes around 1 hour 15 minutes for the program to compile and in the compilation report, i get status as succesful but 97% Slices used up.

How do i optimize this. should i do RMS calculations in RT host? but that was affecting the waveform plot on windows when i had used Express VI ( Amplitude and Level measurement VI)

please let me know.

Thank you. Hema

[WillD]

If you can post a screenshot of your code or attach the VI I could give some better direction.

Quickly, if you put a Single Cycle Time Loop, SCTL, around the comparisons and multiplies and have it exit immediately you will get the benifits of removing some of the enable tree in the compiled code.

If you can divide by a power of two, use a bit shift or scale by power of 2 with a negative constant as the power to minimize space.

For your DC and RMS VIs if your rates are slow enough you can make them non-reentrant such that only 1 copy will be on the FPGA, but called multiple times. This may or may not save space depending on the arbitration logic required.

But really, if it fits and does what you need, who cares?