ni 9871 How much of the 128Kbytes/sec FPGA-to-9871 bandwidth is utilized while the Read Byte method is waiting for timeout

[steve9871]

Hi Becca,

I am running an application that can exceed the 128Kbytes/sec limit of backplane communication between the the NI-9871 and the CRIO-9039 FPGA.

Port 1 is running at 115200 and Ports 2&3 are running at 921.6Kbps... all 3 are independent parallel loops in the FPGA logic

I'm doing the math to make sure I don't exceed the backplane limit.

Each reciever logic poles the 9871 looking for when a byte arrives via the "Bytes at Port" method.... so there can be quite a few reads of the fifo status while waiting for a byte... I need to consider that in my calculations.

Also, for a "Read Data" method, the Labview help says the method will continue to "retry" until either a byte is ready to be read or until a timeout occurs.  Since the minimum timeout is 1ms, I need to know how many backplane access will occur during that 1ms in order to include those access in my backplane calculation.

So in summary, I need to know how often the I/O method retries during the timeout period and how much bandwith is used for each access....

[beccamir]

Steve,

If possible, please create a separate thread. That way it is less confusing for the community as they navigate the forums. Post this information on the new thread so it is informative for the community as they assist you with your question.