question about the sampling rate of the cRIO FPGA (NI9223).

[7600a]

Hello. I'm currently running an experiment using a cRIO-9045 and an NI-9223 (ADC) module and have run into a problem with the sampling rate, so I'm writing to ask for help.

I've created a simple project where I receive data from a function generator with a 30 kHz, 0.1 Vpp input and send it to the host.

However, the actual sampling rate has dropped to 333 kS/s, which is lower than the specified FPGA sampling rate of 500 kS/s.

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019Km2SAE&l=ko-KR

Based on the above information, the sampling rate should be set to a maximum of 1 MS/s when implementing the FPGA VI.

I'm wondering if the DMA FIFO Write part of my VI is the problem and how to solve it.

My FPGA VI has a data type of FXP (24,5) from the NI9223, which goes through a DMA FIFO to the Host. The FIFO settings are as follows:

• Target to Host: Requested Number of elements: 65535

• Host Buffer Depth: 5M

• Host Buffer Read: 10000

Based on the provided Host Front Panel image (with F/G input only on AI0), the sampling rate is falling below the specified rate. It's not exceeding 3 µs.

I'd like to achieve 500 kS/s, if not 1 MS/s. Could you please advise on how to solve this issue?

Thank you for your assistance.

[ZYOng]

See shipping example for the correct implementation of NI-9223 User-Controlled IO Sampling.

Help >> Find Example >> Hardware Input and Output >> CompactRIO >> Module Specific IO >> Analog Input >> NI 9223 User-Controlled IO Sampling