09-19-2013 09:43 AM
sbRIO - is there a way to "pass thru" a bitstream coming in one line and direct it out another? In other words a direct connection, set up Port5/DIO 0 as an input, and setup Port5/DIO 1 as an output. Bitstreams on DIO 0 would pass directly to DIO1.
I tried reading DIO 0 and writing to DIO 1 but that introduces jitter. It seem like an FPGA should be able to have this connection, with out having to clock it through.
Any help would be appreciated, thanks.
09-19-2013 09:48 AM - edited 09-19-2013 09:49 AM
I believe disabling the Sync Registers on the IO Node in the project should achieve this for you. Then just wire the DI to the DO on your block diagram. I don't know what the jitter will be, as I've never had the need to measure it.
From the linked article:
Consider the same block diagram as illustrated above, but now assume the number of synchronization registers is set to 0 for both the digital input and output. The equivalent circuit on the FPGA is shown below.
Here, the digital input signal Digital Input 1 has a direct hardwire connection to the digital output signal Digital Output 1 on the FPGA. The compilation process does not include any control logic to determine when to read Digital Input 1 and write Digital Output 1. In this case, the digital I/O lines are connected to each other as soon as the bitfile is downloaded to the FPGA.
09-19-2013 04:27 PM
T-Rex$,
Thank you!
I disabled the sync registers as you suggested. Made the DIO 0 I/O node a read and made the DIO 1 I/O node a write, then connected them inside a 40 MHz single cycle controlled loop. This worked on a 10 MHz pulse waveform (which is plenty). For giggles I tried it at 20 MHz and the wafveform started to distort.
I also compiled a version, where the connection was made outside of the loop (so that it would only connect at the beginning). But that did not work.
So the bottom line is that the 10 MHz is good for me, thank you.
09-19-2013 04:32 PM