sbrio-9601 IO during FPGA config

[JohnD@P]

We have a sbRIO-9601 with the P8DIO2 output (P3 pin 17) at 1.1V for 320mS after power up even though the output has a 10K pull up to 5V.  After that the FPGA releases control and the signal rises to 5V for about 56mS and then the FPGA starts controlling the output with a 3.3V swing. The waveform is shown in the attachment (tek00000_zoom.jpg - 40mS/div, 5V/div). 

At first, when I saw 1.5V on the pin, I thought the pin configured as a tri-state input, so i added the pull up resistor.  Even with the pull-up resistor the pin is still held at 1.1V, so something is actively driving this pin during configuration.  

Is there a way to disable this output during configuration?  Is there an option to disable the SN74CBTD3384CDGV buffer described on p. 19 of the sbRIO-960x User Guide during FPGA configuration?  

Thanks, 

John D

[JohnD@P]

Oops, a correction.  The voltage was 1.5V without the 10K pullup. The voltage is 2.1V with the 10K pull up to 5V. 

John D

[JohnD@P]

I see this in the Spartan 3 data sheet: 

"The HSWAP_EN input pin defines whether the I/O pins that
are not actively used during configuration have pull-up
resistors during configuration. By default, HSWAP_EN is
tied High (via an internal pull-up resistor if left floating)
which shuts off the pull-up resistors on the user I/O pins during
configuration. When HSWAP_EN is tied Low, user I/Os
have pull-ups during configuration."  

Is there a way to contol the HSWAP_EN through LabVIEW on the sbRIO-9601? 

John D