sbrio best way to exchange data between 2 sbrio fpga

[donomark]

hello,

I'm trying to figure out what could be the best way to exchange data directly between the fpgas of the 2 sbrio 9642ext via digital bus. The communication is unidirectional (from master to slave). 

The 2 sbrio are connected together via flat cable on one of the available jp ports. The data I need to exchange is of real or double type and the amount of these variables are +/- 70.

I need to exchange these informations every 100ms in a deterministic way. Ethernet can't be used for this task and I don't want to use the CPU that is already running full speed managing complex algorithms. So the task need to be done via Fpga.

In the beginning I was thinking to use one or more spi links. Maybe also a parallel link of 8 or 16 bits could work.  

Is there a more efficient way to accomplish the task? 

Thank you for your attention.

Best regards

Marco 

[Logan_081]

Hello Donomark,

Thank you for posting on NI Forum.

I didn't faced with a configuration similar to yours yet. Anyway it seems that the specification that drive you to write on NI forum is the target to exchange data in a deterministic way.

I think that you can go ahead and try to implement your code according to your proposal. in fact i didn't figure out a different technique to exchange data excluding ethernet bus.

Keep in mind that the sbRIO is very similar to cRIO, so you could refer to these resources if you need additional informations about it:

Getting Started with CompactRIO and LabVIEW

RT installation/Getting Started Resources

Let me know if i could provide for additional support on your application.

Best regards

[Spex]

Hi Donomark,

I searched the National Instuments LabVIEW FPGA IPNet (ni.com/ipnet , a one stop shop for finding LabVIEW FPGA IP and examples) and found a communication IP block that may be a valuable starting place for you.  It is designed to use RTSI lines on PXI and PCI FPGA boards to do FPGA to FPGA streaming, but could easily be adapter to work on Single-Board RIO and utilize more parallel data lines.  

The IP is called: 

FPGA to FPGA ACK/REQ Simple Communication Protocol

I hope this helps,