transferring data between a timed loop and normal loop on an FPGA module

[plf]

Is there a way to get data in and out of a timed-loop using a parallel loop, both running on an FPGA module (7831R)?

[thayles]

You could try Memory Read/Write or use global variables.

[plf]

I was unable to compile the VI when I used memory block VIs I created using the memory extension utility but it looks like the basic read/write memory VIs work... so long as I do not place them inside a case structure.

Thanks for the help.

[Ricardo_SR]

Hello,

There are some restrictions on what you can and cannot use within a Single Cycle Timed Loop. One thing you can use to pass data between these two structures are the FPGA FIFOs. 

Ricardo S.

National Instruments