Arbitrary wave generation with LabView FPGA

[Yan_w]

Hello support,

I try to generate two patterns with LUT block from FPGA module.

I initialized the LUTs buy some pattern,  that contain 625 point = 40MHz(FPGA clock) /64KHz and connected LUTs outputs to Analog Outputs AO0 AO1 respectively.

After compellation I run the model on PCI-7833R card  and receive same patterns whit artifacts  but the frequency of these wave forms is 1.5   kHz.

Could you help ?

Attached pls find all project files and printscreen images from scope.

Thank you in advance.

Yan

[Van_L]

Hi Yan,

I took a look at your code.
Your assumption is that the while loop will complete in 1 clock cycle. But it is untrue, the number of clock cycles it executes depends on the layers of combinatorial logic, every layer will take at least 1 clock cycle and some even take longer, for instance, the analog output will take more than 1.

The best case scenario on your FPGA circuit is 4 (a rough estimate) for the circuitry + 2 cc on the while loop. This makes 6 cc to output one data point at 40MHz.

In order to really find out how many clock cycles you are consuming each iteration. You need to do some benchmarking. This is to implement negligible cruitries to find out how many clock cycles exactly is used.

I have attached 2 pictures below which are the common implementation of benchmarking FPGA vi's

[Van_L]

Note: Please ignore my previous message. The forum timed out on me and disabled me from editing it.

Hi Yan,

I looked at your code.
Your assumed that each while loop iteration completes in 1 clock cycle. This is a misconception, the number of clock cycles (cc) a while loop executes depends on the stages of combinatorial logic, every layer will take at least 1 clock cycle and some logic (or nodes) may even take more, for instance, the analog output will take more than 1 cc (perhaps cause it needs to convert from digital to analog)

The best case scenario on your FPGA circuit is at least 4 cc(a very rough estimate) for the circuit plus 2 cc on the while loop. This makes minimum 6 cc to output one data point at 40MHz.

To really find out how many clock cycles you are consuming each iteration. You need to do some benchmarking.
FPGA benchmarking is implemented by adding extra cruitries (will not add overhead to the original design) to find out how many clock cycles are actually used from start to end of one while loop interation.

I have attached 2 pictures below which are the common implementations of benchmarking FPGA vi's



The top figure illustrates one way to extract the loop period. To implement, you only need to add the tick count, subtract and a shift register as shown.

The bottom one is to calculate the number of cc instead of time.

After you obtain these values, you can then change the number of samples on the look up table and achieve your desire frequency.

I hope this clears things up

Good luck


Message Edited by Van_L on 03-12-2008 08:41 PM

Message Edited by Van_L on 03-12-2008 08:42 PM

Message Edited by Van_L on 03-12-2008 08:46 PM

[Yan_w]

Dear Van_L,

Thank you very much for your help.

I understood the concept.

King regards,

Yan