Razaq wrote:
when I first tried this, it was with USRP 14.0 driver (the first driver version with USRP-RIO), and it did not work (although the triggering logic in the code seemed fine). And when I upgraded to newer versions of the driver (now USRP 15) it wored perfectly, so I assumed it is a bug in the old driver version.
Some more information/background: the Sample Project (SPr) has evolved over releases to address common use cases, but the SPr cannot perfectly address *all* use cases. Making simultaneous Tx and Rx easier is a continual goal/work-in-progress.
The FPGA's triggering logic has not appreciably changed, but the top-level Host has changed for Full Duplex. Older versions of the SPr had an ordering dependency between the Rx and the Tx side for Full Duplex. For example, setting Rx's start trigger to Tx Start Trigger but Rx fetches before Tx writes; this would result in the Tx start trigger never firing, hence the Rx start trigger never firing, hence the Rx fetch would timeout.
TL;DR: Ensure the master side (either Rx or Tx) triggers before the slave side consumes that trigger in a blocking fashion.
