Can you change pwm period in veristand workspace?

[joedowdle]

I am generating PWM's in Veristand through an FPGA.  It works just fine as is and I can vary the duty cycle in the VeriStand workspace and it responds appropriately.  Now I'd like to be able to vary the period of the PWM's without having to go back into the system def file to edit it.  Is there a way to add a control to the workspace to do this or will I have program this to be done on the FPGA?  My FPGA is close to max capacity so I need to try to minimize the amount of code I add to it (I'll be going through and doing some optimization once all features are working properly).

Thanks for the help.

[StephenB]

Unfortunately the standard out of the box veristand example FPGA for PWMs doesn't have this functionality. However you can do some tricks to make it work great. See here: https://decibel.ni.com/content/docs/DOC-16699

[joedowdle]

That looks like it would work pretty well.  I have one question though that maybe you can answer.  Do you know if the square wave generator uses up more FPGA resources than say just the PWM Out subVI that I am using?

[StephenB]

I've wondered that myself before.... I'm not sure. I'd have to do a test. Let me know if you find out

[joedowdle]

To kind of answer the question at hand... when I compiled my code with the square wave generators in place of the PWM Out subVI it it used slightly less resources on the FPGA.  I can't be 100% sure if that was just due to the one change or some of the other changes I made as well, but it might be helpful to know/look into for future programs.