VeriStand SDF - transfer did not complete error

[joedowdle]

Hey everyone,

So I had an issue where it couldn't connect to the FPGA when trying to deploy the SDF in VeriStand.  The problem with that was that I had the wrong reference (referencing RIO1 when it was RIO0 in MAX). So I fixed that and now I get this error.  It says that the transfer did not complete within the timeout period or within the specified number of times.  What could cause this?  When I remove the FPGA stuff from the .vssdf it deploys just fine, but I get this error when I add it.  I'm not sure what would cause this to happen.  Any ideas?

I have included a screenshot of the original error message.  Thanks.

[KHartley]

Hey Joe,

Are you trying to deploy custom fpga code or one of the sample code pieces?

Can you try deploying sample code? Do you get the same error?

Can you try disabling part of your FPGA code to see if you can upload a smaller section of it?

I found another issue from a customer but the resolution gets vague, I'll need to follow up with another AE to see if he ever found out the exact details of the resolution.

Thanks,

[joedowdle]

I'm still not sure what the problem is but I moved everything to another project and it has worked in that one.  Ever setting is identicle between the two projects that I can tell but for some reason it doesn't work in the one.  I guess I'll just let it be unless I run into it again.  Thanks for the help.

[StephenB]

that usually happens for one of three reasons:

1. you defined a different number of DMA packets in your FPGA XML (*.fpgaconfig) than the FPGA code is actually reading and writing
2. You have multiple DAQ and/or FPGA devices in your system definition and your chassis is not identified in Measurement & Automation Explorer (find the controller, expand hardware, find the chassis and right click identify the controller then the chassis)
3. You have multiple DAQ and/or FPGA devices in your system definition and they are in different bus segments of your PXI chassis without the triggers being routed between the bus segments on the PXI backplane. You should go into the system definition, find the master DAQ/FPGA device (click chassis to find out which one it is) and then go into MAX and select the chassis and select to route triggers away from the bus segment containing your master device