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Error deploying to cRIO target with Scan Engine bitfile

I have a VeriStand project that deployed fine.  I added an FPGA bitfile to the project (just commands 2 cards to do resolver demod) and it worked fine.  No problem deploying.

 

I updated the resolver code and simply changed the size of some fixed point values to increase my demod resolution.  Updated the bitfile and went to deploy... and it threw an error.  Text is below.  I know the new bitfile will deploy to the target because I've tested it from my LabVIEW project.

 

Here are the things I've tried:

  • Uninstalled / reinstalled VeriStand engine on cRIO target
  • Manually went in to the nivssdf xml file and cleared out all references to my bitfile.  After this the project deployed no problem - until I added my bitfile again.
  • SSHd into the cRIO and manually cleared out the deployed files.
  • Went back to the first version of the file. I had to repeat steps 2, 3 but then it deployed again fine.
  • Repeated steps 2, 3 again and switched to new bitfile.  Fail to deploy.
  • Recompiled new bitfile because why not?
  • Restarted my cRIO multiple times.

 

I'm out of ideas.  Anyone have any suggestions?

 


• Preparing to deploy files to the targets...
• Starting download for target cRIO-9039...
• Opening WebDAV session to IP 192.168.1.15...
• Processing Action on Deploy VIs...
• Setting target scan rate to 1000 (uSec)... Done.
• Gathering target dependency files...
• Downloading MultiPlat.nivssdf [452 kB] (file 1 of 5)
• Downloading MultiPlat_cRIO-9039.nivsdat [300 kB] (file 2 of 5)
• Downloading CalibrationData.nivscal [5 kB] (file 3 of 5)
• Downloading MultiPlat_cRIO-9039.nivsparam [0 kB] (file 4 of 5)
• Downloading Multi_Resolver_FPGA_.lvbitx [5483 kB] (file 5 of 5)
• Closing WebDAV session...
• Files successfully deployed to the targets.
• Starting deployment group 1...
• Target PXIe-1085 is online.
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error 7 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW: File not found. The file might be in a different location or deleted. Use the command prompt or the file explorer to verify that the path is correct.
=========================
NI-488: Nonexistent GPIB interface.
=========================
NI VeriStand: NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi >> NI VeriStand Engine.lvlib:VeriStand Engine.vi >> NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi >> NI VeriStand Engine.lvlib:Initialize Inline Custom Devices.vi >> Custom Devices Storage.lvlib:Initialize Device (HW Interface).vi

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Sending reset command to all targets...
• Shutting down VeriStand PC Engines...
• Stopping TCP loops.
Waiting for TCP loops to shut down...
• TCP loops shut down successfully.
• Unloading System Definition file...
• Connection with target PXIe-1085 has been lost.
• Connection with target cRIO-9039 has been lost.


 

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Message 1 of 4
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Does your bitfile have an updated filename? Check to make sure it is correct in the .fpgaconfig file. http://forums.ni.com/t5/NI-VeriStand/FPGA-personality-addition-to-VeriStand/td-p/1428516 

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Message 2 of 4
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Bitfile has an identical name.  Just recompiled with extra precision on the fixed point.  I'm also adding the bitfile through the EtherCAT custom device... I don't have a .fpgaconfig file.

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Message 3 of 4
(2,912 Views)

Interesting. I wonder if VeriStand has constraints as far as fixed point precision. Did you change it from a default like 16, 32 or 64 bit to something else?

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Message 4 of 4
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