HP Loop duration increases with two FPGA on PXIe-1082, HP count increases

[Rokot]

?? There is no problem with the VeriStand FPGA Interface. There is a problem with a VeriStand-project with more then one FPGA.

[Jiri_K · Accepted solution]

My guess is that the synchronization doesnt work.

Either the clock is not shared on trigger line. Or is not imported on the slave FPGA. Or wrong set of NIVS FPGA template vis were used...

[Rokot]

Yes, there is a difference in the FPGA code between the project (C:\Users\Public\Documents\National Instruments\NI VeriStand 2016\FPGA) and a project that I created with the project wizard under VeriStand Custom FPGA Project that comes with the VeriStand FPGA-Based Interace I/O Tools http://forums.ni.com/t5/NI-Labs-Toolkits/NI-VeriStand-FPGA-Based-I-O-Interface-Tools/ta-p/3493285.

VeriStand Custom FPGA Project:

Timing:

So there is no Timing/Sync.

C:\Users\Public\Documents\National Instruments\NI VeriStand 2016\FPGA:

[Jiri_K · Accepted solution]

Yep. On the first picture is visible, that the set of vis was cRIO/sbRIO version. You need to use the set for PXI...