Model Parameters causes Model count increases

[R.Kaszubiak]

Hi,

Software platform : NI VeriStand 2012

Chasiss cRIO 9082RT + NI 9155

I have two nivssdf :

- ALL : which contains :

    * three models (model A with decimation = 1 ; model B whith decimation = 5 and model C whit decimation = 1)

    * two FPGA

    * two custom devices

- Light: which contains :

    * one model (model B whith decimation = 5)

    * two custom devices

PCL = 1KHz and model B is a simulink model compiled into a dll which has several parameters and signals.

When I deploy "Ligh" nivssdf, there is none FPGA running, the PCL is automatically synchronized, and model count doesn't increase.

When I deploy "All" nivvsdf, synchronization is done by one of the RIO and i see Model count increases.

When I redeploy it without model parameters simulink, i doesn't see model count increases.

Parameters can have an effect on the Model Count increase?

Have you got any idea about that problem?

Remark : HP count is stable and  = 0.

R. Kaszubiak

[sabri.jatlaoui]

Hello R.Kaszubiak,

When you’re talking about model count, i presume it’s referring to the HP count.

HP count return the number of times the Primary Control Loop reported being late.

With your light nivssdf, you’re not deploying anything on your FPGA, it’s only simulation. When you’re deploying on FPGA, it's doesn't suppose to have the same behavior. For example, in your case you have probably chosen PCL time too small for the FPGA card to run it.

Best regards.

[R.Kaszubiak]

Thanks to answer.

When i talk about model count is not hp count but model count indicator which is rising.

My PCL runs at 1000Hz and my actual loop is 1000Hz +/-10us so my FPGA runs correctly.

After several tests, It seems that when my ALL nivssdf is executing, CPU usage is high and the model count will be a consequence of that but normally, it could be HP count which could increase.

R. Kaszubiak