PCL RATE VERISTAND

[MohammadOkour]

Dear all.

I'm working on Hardware in the loop simulation project , we already have a system with some kind of controller and its working fine , now we are trying to make a new system using ni veristand and crio9068 .

I have implemented the simulink model , configured the settings and map the I/O data and also used RS232 custom device.

My problem is the system is not running as real time i tried to compare something between the old system and the new system and i got different results.

i tried to use the same frequency for the model and to set the PCL rate as the model ,also more than model  and it doesn't work.

i tried both parallel and low latency execution modes and i got results slower and faster than it supposed to be .

I'm really confused xD.

any idea what is happening with me ?

[okubik]

Based on given information, it's hard to point you to the right direction. It would help if you answer the following questions:

What is the target PCL rate?

Does the HP/LP count (or model count) grow over the time on the running system?

The RS232 is expected to run synchronously?

What Custom devices are used? I guess Instrument-Custom-Device, and for I/Os SEECD, FPGA-Custom-Device or implemented Custom FPGA Personality? What else?

What is the CPU and memory utilization of the cRIO during the execution?

[MohammadOkour]

Thank you for your response

1-The PCL rate is 1000Hz, i also tried different values such as 50 , 100 , 200 HZ

2-HP is increasing , model increased and remained zero depending on whether im choosing low latency or parallel execution

and for the custom device yea the https://github.com/NIVeriStandAdd-Ons/Instrument-Custom-Device is used.

btw the model frequency is 200 HZ 

and I'm sending and receiving the data through the custom device at 20ms

for the I/O data i have mapped the in/out data to and from the model with custom device send and receive ports

and for the utilization im not sure i will check it tomorrow and replay this post with updated answer

[jalfonso]

I propose to  diagnose where is the problem before try to fix it.

Open workspace and put numeric indicators linked to.

   - Targets/Controller/System Channels/HP Count

   - Targets/Controller/System Channels/LP Count

   - Targets/Controller/System Channels/Model Count

These values are counters of time outs in High Priority, Low Priority and Model loops.

In case Model Count incresases, you need to profile the code of your model to avoid delays. In case you have got some models, you can check the duration of the calculus of the model using 

   - Targets/Controller/Simulation Models/XX_Model_Name_XXX/Execution/Time Step Duration.

[okubik]

Well,

for diagnostics you can play with the Warmup Time parameter on the Controller Configuration Page. I would check what is the CPU and RAM profile for you model. I would set the warmup to zero and observe counters + resource usage using the Custom Device for monitoring VeriStand performance. Also check if you set correctly model decimation and it's execution time reflects the RT system execution time (if it doesn't run faster or slower). As next I'd exclude all unused model IOs and parameters as well as any other unused physical IOs.

[jalfonso]

You can use the tool "console viewer" to check the cpu use. This tool is allowed by defect in the veristand Project.

You can start the tool from "Project Explorer->Tools->Workspace Tools->Console viewer"

[MohammadOkour]

I tried different cases using Low latency and Parallel modes , LP ,HP counts increases in both modes while in the low latency mode the model count is zero comparing to increasing count in parallel mode.

for the cpu load if i understand it well i checked the NI MAX after i deploy my project it was over 92% 

and for the CPU interrupt load it was 27%

i tried to use the console viewer but i cant connect when i try to press connect the led stay off and never connect.

[MohammadOkour]

I have added indicators to see these values.

But my question is  what is the best case for these numbers?

i read that LP and HP counts are related for the number of times that the data processing loop and the PCL delayed

and for the model count its the number of times that the model haven't executed .

I'm not sure if i got it right but i think these counters should be zero?

[HoussamK]

The late counts (HP, LP and Model count) determine if any of the indicated loops are late. If one of these loops is late, then it means that it did not complete in the specified loop time. If it did not complete, it will skip iterations until it finishes (NOT GOOD!). You want these all to be zero.