Timing problem between VeriStand and model

[HScho]

Hi,

I have a problem with the timing of my model and VeriStand. My model is very simple and is a state-space model for a DC motor. Attached is the model and the simulation settings. The data from or to the model are from a custom FPGA personality.

The step size of the model is 0,001s so the target rate of my controller in VeriStand has to be 1000Hz, am I right?

The problem is that I cannot run the model in VS with “Final Time” set to “Inf” because then I do not receive the values of the model and if I undeploy the System Definition File VeriStand freezes at “Waiting  for models loop to shut down…”. Even if I put a control mapped to the “halt model”-control and activate it, the model does not stop.

I have also put a numeric indicator to the system channel “Model Count” to see if the model finishes late. Only if I set “Final Time” to 2 the model does not finish late but my values are not correct.

Is there a way to use the model with “Final Time” set to “Inf” in VeriStand? Is there an alternative how I can use the model with correct timing?

Thank you!

Regards,

Hscho

[ClaudioH]

Hi,

I work with models time set to inf at 5 kHz rate.

Did you try to deploy and run the model without map the inports and outports to the FPGA?

Set the inports default values before run the model to avoid crash.

Cheers,

[HScho]

Hi,

what do you mean with "models time set to inf at 5 kHz rate"? If I set the final time of my model to "Inf" and the target rate of my controller to 5kHz there is still the same problem. I cannot stop the model loop, I tried with the model control and with a boolean control to "Halt?" in the simulation model.

I tried to deplay and run the model without mapping to the FPGA also still the same problems.

So I tried again and the model count only at "Final Time" set to 2 does not increment. Additionally in the "Timing Parameters" the box "Synchronize Loop to Timing Source" must be unchecked.

Can you explain me this behaviour? Is it problem of my model? 

And what do you mean with "Set the inports default values before run the model to avoid crash.", I have no crash.

Thanks,

HScho

[StephenB · Accepted solution]

HScho,

I haven't looked at your model zip file but based on your last post it makes me think your model is written in LabVIEW and you have a control design and simulation loop in your model. This is incorrect. You should not have this loop in your model. Remember that NI VeriStand is the loop. Just compile the contents of the loop as a simulation subsystem.

[HScho]

Hi Stephen,

that sounds logical. I have now made the model with a control subsystem and I can build the VeriStand model without errors (I have attached the new VI). But if I use it VeriStand and place a "model control" there is a "Invalid Mapping" message inside. Even if I do not map the model to the FPGA  this message occurs in the control. If I try to stop the model with the model control in the RT screen appears following message "NIRT_Sched error = -2330 , in[0] = 0.000000, out[0] = 0.000000" and the number in the control shows "NaN".

Here a picture:

So my model still does not calculate "Ang Speed", I have also changed my PXI-8196 controller with a faster PXI-8110. I have also tried to use the model with 500Hz (step size 0.002) without success.

Thanks for your help so far, I hope you guys have some more hints for me.

Regards,

HScho

[HScho]

Ok very strange....

I have just put the control subsystem in a new VI as subVI. Now I get the Ang Speed values and my simulation is working. In the model control is still the "Invalid Mapping" message but the values are correct.

I have attached the working model VI. So Stephen your hint was correct and made my project working, thank you very much!!! 

If someone has an idea why there is still the "invalid mapping" it would be nice to know why this occurs?

Regards,

HScho

[StephenB]

HScho,

I'm not sure how you're compiling this model VI. When I try to compile it, I get an error for unsupported data type(s). Looking at the "state-space model" input parameter... there are several strings and 2d arrays inside that cluster. Strings are invalid parameter types for NI VeriStand. 2d Arrays are currently unsupported. Instead, I recommend changing this cluster to a cluster constant on the block diagram and bundling in the non-string parameters you need to set at run time. You can also flatten your 2d arrays into 1d arrays until we add 2d array support.

Also, if I go to operate -> configure simulation parameters... I see that this subsystem has the "synchronize loop to timing source" checkbox set on the timing paramters tab. Remember that NI VeriStand will be the timing source, so you should not check this box.

[HScho]

Hi Stephen,

you have to use the VI "Dc motor model VeriStand" in the zip from my last post. The VI you used was just a experiment.

I will give it a try with the synchronization disabled and will post the result here.

HScho

[StephenB]

Ah, sounds good. Glad you're making progress!