reset all outputs to initial values

[TTRD]

Hi,

in our case, a VeriStand project is running on a RT machine with cRIO-I/O.

Is there a possibility to reset all outputs to the initial values while the project is running? (I don't want to restart the real-time system or deploy the project again because that consumes too much time.)

[thumble]

hello, maybe you could run a real-time sequence or CSV file, or trigger a procedure to do that. In any of these cases you'll have to write some code to set all your output channels.

[PhilipDeppe · Accepted solution]

Hi,

you can create an alarm which calls a reset procedure. The Alarm can be mapped on a Boolean Button on the Workspace. Or you can call a RT Sequenze to reset your values.

Best Regards,

Philip

[TTRD]

A button on the workspace sounds good. I think I will try to define a procedure. The only problem is that I have to reset about 100 variables. However, it seems as if I can generate the XML-code of the procedure from a FPGA config. I'll get back if I succeed or encounter a problem.

[TTRD]

Works fine. Thank you both for the tip. 🙂

[PhilipDeppe]

Nice 🙂