Logical multiply instead of pause trigger

[AlexanderRyabov]

Hello all!

Can some one help me with gating counter with another one,

i want to produce modulated timebase, first counter generate pulses in continuous mode, and another one does the same, but with lower frequency,

for example f1 = 20Hz, f2 = 0,1 Hz. The first counter gated with another one, are there any option to temporary stop counter1 when counter2output is in logic low state, i want produce timebase OUT = [ctr1out] [logical multiply] [ctr2out], not pausing.

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Alexander.

[Kevin_Price]

Here's an idea I don't think I've tried, but I *think* will work.  You'll need a 3rd counter whose output will be the

timebase that behaves more like you want.  You mentioned a 6602 in another recent thread, so hopefully

you've got another counter available.

The 3rd counter would be configured for retriggerable single pulses using the 1st counter's rising edge as a

trigger signal.  The 3rd counter should have the same pulse width (high time) as the 1st counter, and probably

a very minimal low time.

Each rising edge of the 1st counter will produce a fixed-width pulse on the 3rd counter.  So now, even when

the 1st counter gets paused in an output-high state, the 3rd counter will return low after its single pulse and

not pulse again until the 1st counter gets un-paused long enough to produce another rising edge.

-Kevin P

[AlexanderRyabov]

This will be good for a simple modulated timebase, but i'll do a complex timebase. Probably i have to make an external TTL summator with IC chip (logic AND gate).

Configuring 6602 for logical operations will be the easest way but miracles do not happen 😞

[James-D · Accepted solution]

Hi AlexanderRyabov,

If you would like to produce a modulated timebase you should be able to achieve this by connecting the outputs of counter 1 and counter 2 to the source and gate of a third counter. The low frequency counter would be connected to the gate and would act as the enable/disable signal for the high frequency counter that is connected to the source. The result would be when the low frequency counter pulse is high, the counter 3 output will exhibit the high frequency counter pulses from counter 1 and when the low frequency counter pulse is low, the counter 3 output is low for the duration of the gate's (counter 2) low pulse. This is equivalent to a logical multiply of the two counter signals.

Here is a link on how to route the outputs of two counters to the gate and source of a third counter on the board you are using:

http://zone.ni.com/devzone/cda/epd/p/id/2109

I hope this information helps!

Regards, 

[AlexanderRyabov]

Hi James,

it seems to be true,

will try it!