If I understand your question correctly, you wish to use or generate an onboard clock to act as your sample clock for the buffered event counting task. This will obviate the need to wire up an external clock signal to a PFI line.
The best way to do this is to use a second counter to generate a continuous pulse train and then route the output of this counter as the sample clock source for the buffered event counting task. You can do this pretty easily by using two of the shipping examples in conjunction with each other.
First, open the Gen Dig Pulse Train-Continuous.vi shipping example and set the counter channel to ctr1 with the Frequency set to the desired sample clock rate. Second, open the Count Digital Events-Buffered-Continuous-Ext Clk.vi shippin
g example and set the Sample Clock Source input to Ctr1InternalOutput. If you run the two VI's, the pulse train from counter 1 will act as the sample clock for the buffered event counting task on counter 0.
