synchronized pulse suppression with 6601?

[grubin698]

Hello all,
I'm trying to get a counter-based application set up using a PCI-6601 counter board. I haven't done NI DAQ in years, and this is my first foray into DAQmx. I feel like I'm really fumbling around here. My current approach is to find an example that has part of what I want to do and cobble it together with parts of other examples. It's a lot of trial and error (mostly error). I'm not finding the DAQmx Help particularly helpful either. It explains how to call each function, but that's really only helpful if you know which function to use in the first place. Any advice on where to start?


In case anyone has any insight, here's what I'm trying to do:
1. Counter0 generates a pulse train at a constant rate. This represents the system trigger.
2. Counter1 generates a pulse train which is synchronous with Counter0 and delayed from it.
3. Counter1 uses the Pause Trigger Property so that it is suppressed when one of the DIO lines is high. When the DIO line returns to low, it Counter1 pulses should come back in the same place relative to Counter0.

I can get 1 and 2, but not 3, or 1 and 3, but not 2.
If I make Counter0 and Counter1 part of the same task, then they are synchronous, but the Pause Trigger property seems to only work on tasks, not channels, so I can't apply it to Counter1 without applying it to Counter0.
If I make Counter0 and Counter1 differents tasks, so I can apply the pause to just Counter1, I lose synch between the two counters. I tried using DAQmx Start Trigger (Digital Edge).vi to sync the Counter1 task with Counter0, but get an error that I can't use both Pause and Start triggers in the same task. I then tried using the ArmStart property instead of the VI mentioned above. This worked fine, until I unpaused; Counter1's pulsetrain was then synchronous with the unpause, rather than Counter0.

Can anyone offer any advice, or at least point me toward some useful resources? If I remember right, it was this confusion of how to find the right tools that led me to use traditional DAQ for my last DAQ project, even though DAQmx was available at the time.

Thanks,
Gary

<cross posted in LAVA>

[grubin698]

A follow-up stupid question: 

My board has a Counter N Gate Signal.  Searching for Gate in Find Examples comes up empty.  DAQmx Help explains that a gate signal is use for starting or pausing the counter (great!), but it doesn't tell me how to configure the channel to use the gate.  LabVIEW Help, where the descriptions of the DAQmx VIs live, doesn't have any info on configuring gates either (at least not though the search).  

I'm also finding things in the LabVIEW help that look like they might do what I want (i.e. Trigger properties, but then when I try to use find those properties, they don't seem to be an option (such as Reference: Digital Pattern: Trigger When).

This is very frustrating.  Do I need to pitch DAQmx and do this via traditional DAQ?

Are these limitations of the 6601?

Message Edited by grubin698 on 05-12-2009 12:17 PM

[Abram_R]

Hi grubin698,

I noticed at in the thread that you cross posted to that you have contacted NI support and had reached a solution. Do you have any additional questions about this issue?

For those that are reading this thread and have similar questions, one good example program in using pause triggers for counter boards can be found here: http://zone.ni.com/devzone/cda/epd/p/id/3575

The way the counter gate signal gets used will depend on the kind of task you are using. At the basic level, a counter will count the rising edges of the source signal if the gate signal is high, and will stop counting when the gate signal is low.

-Abram

[grubin698]

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Abram R wrote:

I noticed at in the thread that you cross posted to that you have contacted NI support and had reached a solution. Do you have any additional questions about this issue?

---

The solution I reached was that it would likely be quite difficult to do within LabVIEW/DAQmx, and instead I used external circuitry.  So, I basically punted on the problem...

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Abram R wrote:

For those that are reading this thread and have similar questions, one good example program in using pause triggers for counter boards can be found here: http://zone.ni.com/devzone/cda/epd/p/id/3575

---

This example is for input counters.  I'm looking for that type of functionality on output counters (continuous pulsetrain generation). Does it work for that too?

Gary

[Abram_R]

Hi Gary,

The pause trigger will work well for your application, and I don't think the Arm Start Trigger is nessesary. My example that I posted probably wasn't the best choice for you. I've thought about your problem more and experimented a bit, and I think you can exploit the fact you can have multiple pause triggers on the same counter output task and use two pause triggers and an additional counter to perform your task.

Here's how it would work.

1. The additional counter is configured such that it produces a retriggerable single pulse output task that is triggered off the falling edge of your DIO line. This will be used to time the delay between your counters.

2. The Counter 0 output channel will have one pause trigger off of the DIO line. 

3. The Counter 1 output channel will have two pause triggers. One will have the source terminal be the DIO line and the other will be off of the internal output of the counter performing the single pulse generation task. When the DIO line is asserted than deasserted, the generation will be first paused by the level of the line itself, and then it will be paused again because the falling edge of the DIO line will trigger a single pulse output that is wiring to the second pause trigger.

Here's a KB on a very similar process: http://digital.ni.com/public.nsf/websearch/8F070C8CFDFEC0FA86256F7A00141425?OpenDocument

I don't have a counter/timer board with enough counters handy, so I haven't been able to test my solution out. This proposed solution also assumes that you can pause your Counter 0 output. If you can't for your application, then your external circuitry might be the best bet.