7811 response time

[9845567540]

I want to set a digital output to high and back to low in a specified time of 100ns. The rise time of the signal should be <20ns. I learnt from another post that it will take 60ns for the data to appear on the line.

Can I compile the code in 200MHz derived clock and acheive the required timing? What is the maximum rate to which i can go? We are planning to buy this card if it satisfies our needs.

"What is the response time of the 7813R?"  This depends on the FPGA speed at which you compile your logic.  Once you write a value to the LabVIEW FPGA I/O Node, it will take two ticks of your FPGA clock for the data to pass through its synchronization registers.  There will also be ~10 ns for the front end analog circuitry to respond.  This of course may increase if you are driving higher capacitance.   So in summary if you compile the FPGA code at 40MHz, then once you write a value to a LabVIEW FPGA I/O Node, it will take around 60ns for the data to appear on the line.

[srm@viewpointusa.com]

the propagation time is the same for high to low and low to high.  if you code a 100 ns pulse, you will get a 100 ns pulse.  rise time and fall time should be within your specs.  however, if you need more or less, your granularity will be 25 ns.  not sure if you can include i/o with a higher derived clock.  if you are trying to react to an external event like a clock, the propogation may hurt your response time.

[9845567540]

Thanks for the reponse. I kinda measured the rise time and fall time on a scope for 8 MHz clock that i coded on LV FPGA. The measured value was around 45-50ns. I think it is possible to use a SCTL with a derived clock and acheive even lesser rise times. But I don't know how to do it. May be I need to experiment on the SCTL.

[srm@viewpointusa.com]

i don't believe that using a derived clock will affect the rise or fall time.

[9845567540]

The 781x user manual says that the rise time of DIO signals is 12.5ns. I wonder how they have arrived at this spec?

[srm@viewpointusa.com]

12.5 agrees with what I have seen.  maybe i will do another quick test to verify.

[srm@viewpointusa.com]

I just measured a 7833r.  8 ns rise time 6 ns fall time into a scope load.

[9845567540]

which connector block and cable did you use?

[srm@viewpointusa.com]

TBX-68 and Sh68-C68-S.  DIO0 to DCOM

[9845567540]

I used the same cable and a CB-68LP. I used the normal while loop to create the 8 MHz clock. I still don't get how the measurement error was induced. There must be some capacitive elements coming in the way.