HSDIO PXI-6552 DDC CLOCK OUT to STROBE ?

[engwei]

Hi,

 . Thanks for clarification from you guys. 

[DJ_L.]

Hey engwei,

Sounds like you have a better understanding of what is going on. I just wanted to add a couple of documents to this thread to help further explain a couple of the topics that you asked about. First, for your question about why in some of the HSDIO example programs it talks about connecting DDC Clock Out to Strobe, here is a good DevZone article called National Instruments High-Speed Digital ATE and Stimulus Response Features, and in there it talks about using external connections to account for Round Trip Delay. This document does a good job of explaining how you can send your clock along with your data so that you sample the correct data at the right time. Next, for your question about signal integrity and where to probe, check out the following documents: Termination and Cabling Considerations for HSDIO and Proper Termination for High-Speed Digital I/O Applications. I hope this helps add to what you might have already figured out. Thanks, and have a great day.

Regards,

DJ L.

[engwei]

Hi,

Thanks to your information. 

Let me summarise here. Please feel free to leave any comment or suggestion here.

Original post:

1. The datasheet snipet comment should be "Strobe signal can only be routed to Strobe cable"

Additional question: (Cable termination problem)

1. While DDC Clock Out (flying lead cable) is connected to Strobe cable as acquisition clock, there is no way to "share" the clock to application board. This can be proved from the distorted signal at the DDC Clock Out terminal. As this is the "destination" for the application board, the clock signal sourcing out at this point is not suitable. 

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There is another question, related to the scenario describe in this post, open a new post may confusing.

My application board powered by 1.5V and 3.3V power domain.

And I start the signal generation to the board, at the same time the clock signal started too.

Situation:

DDC Clock Out cable is connected to the Application board clock input and Strobe cable.

Power supply set to: 1.5v, 3.3v

Then something weird happened on my Agilent power supply, the reading become:

Power supply (current limit at 300mA)

3.3V (91mA)

1.648V (47mA)

If disconnect the Strobe cable (both signal and ground), the reading is:

Power supply  (current limit at 300mA)

3.3V (94mA)

1.5V (13mA)

Have some1 there experienced this before ? Any idea about it ?

Message Edited by engwei on 01-08-2009 10:08 PM

[Keith.Shapiro]

Hi engwei,

Without an understanding of what is on your application board, it's almost impossible to speculate as to why plugging or unplugging a cable might cause a change in power consumption.

Also, you are correct - there is no way to directly share a clock without proper termination.  You can either receive the clock on your application board, and use a clock buffer IC to split the single clock into two point-to-point clocks, or you can use a system synchronous approach on the PXI-6552 with round-trip-delay compensation to make your acquisition session line up with your generation session without needing to drive a clock back to the 6552.

Ultimately, you may need to perform timing analysis for your system in order to figure out the best settings to use on the 6552.

Keith Shapiro

National Instruments R&D

[engwei]

Hi Keith,

Thanks for your reply.

Ya, I agree with you that I may need a clock buffer on it ..

For my case now, the application board is just a direct connection to the pin of IC. My purpose is to generate a pattern and acquire back the data, it is a jtag test. 

From your reply, 

"or you can use a system synchronous approach on the PXI-6552 with round-trip-delay compensation to make your acquisition session line up with your generation session without needing to drive a clock back to the 6552. "

But when I run the error location - hardware compare example,

by looping back the DIOs,

I have notice that the result is different between the one using the OnboardClock as acqusition clock and the one using Strobe Clock (exported from DDC Clock cable) as acquisition clock. Both triggered by StartTrigger which routed through PFI2-PFI3.

Just to confirm with you that, the result should be the same ?

Thanks a lot.

[Keith.Shapiro]

Apologies for the delay in response.

Using Strobe wrapped back from DDC CLK OUT as a clock source for acquisition is *not* the same as using onboard clock for acquisition.  There is a definite difference in phase, as well as in setup/hold time requirements to the connector.

 I'm not sure I understand your situation enough to give you any more guidance.  If you can explain what it is you're trying to do, perhaps I can help you with a solution.

Thanks,

Keith Shapiro

National Instruments R&D

[engwei]

Hi Keith,

Thanks for your reply ..

Not understand with this "

Using Strobe wrapped back from DDC CLK OUT as a clock source for acquisition is *not* the same as using onboard clock for acquisition.  There is a definite difference in phase, as well as in setup/hold time requirements to the connector.

"

All these timing should be already compensated by the star trigger triggered by data active event rite .. ? Maybe I need to study more .. Anyway, thanks. 🙂