Slave SPI

[Uzi]

Hi,

I have the USB 8451 but it only work as a master.

I need a device as a Slave SPI

Any recomandations??

Uzi

[stilly32]

Hey Uzi,

It will depend on what you need your slave to do, and at what rates your clock will be running. If you just need the slave to send back predetermined data on the clock edges, we can do that with a device with correlated DOI(like M-series devices). M-Series can output correlated data at up to 10Mhz with an external clock. Those devices do support change detection so you could write/read on the falling and rising edges. If you need it to truly simulate a slave device and act off of commands, then you'll have to allow enough delay for the slave to read in the serial data, translate it to the appropriate word and generate the appropriate response - depending on what rate and time between your commands this can be very hard over the PCI or USB bus and up through the OS.

If you need a more deterministic solution, one of our FPGA devices would definitely be able to act as a slave device. Again, it would depend on the rates for the performance though.

Hope this helps, let us know if you have additional questions about the devices or how to implement the communication.

Cheers,

Andrew S 

[Uzi]

Hi Andrew ,

Thanks for the quick response,

 The salave SPI is just to validate the spi lines at speed up to 10MHz in the begining and later on i will do tests in up to 25MHz

The M series could be good for up to 10MHz.

My Application is not deterministic but will need to work at high speed

Do we have more soloutions?

thanks, Uzi

[stilly32]

Hey Uzi,

For 25 Mhz, you would want to look into the NI 6537, or one of the HSDIO boards. In order to act as a slave, you need a board that supports change detection, which the 6537 does. One of the FPGA boards may be able to achieve those rates, but I would post on that forum if you are interested in a definitive answer. If you are looking at purchasing, I would contact the Technical representatives at www.ni.com/contact - they're good at spec'ing out systems and making sure you have all the right peripherals.

Cheers,

Andrew S 

[Priyatham]

Hi Andrew

I have a question on similar lines ...... Im using PCI 6551 to act as a SPI Master to my DUT , but after one point the DUT takes over as the SPI Master and I have to respond as a slave sending predetermined bytes on the clock edges of the SPI(which is 7.5 MHz). I was wondering if I can achieve this with 6551. Plz help.

Thanks,

Priyatham.

[HSTech]

Uzi,

You may want to look at a new product that NI just released about a month ago - the NI PXI-6581R.  This product is based on LabVIEW FPGA - so you would be able to program the FPGA to respond in any way that you want.  But it also has a very flexible digital front end that can work at clock rates up to 100MHz at many different voltage levels between 1.8V and 5.5V.  It may be exactly what you need.

 https://www.ni.com/en-us/support/model.ni-6581.html

Hope this helps,

Charles

[Priyatham]

I have one question regarding being able to act as a SPI slave. The issue in simple words is that, I want to trigger the generation engine on a signal while acquring the same signal. I want to start the dynamic data generation engine(SPI Slave dataout) on the chip select trigger, but at the same time I also want to acquire that signal so that I can view it in a graph along with the other acquired signals. To acquire a signal it should be connected to a DIO line and I cannot trigger my generation engine from a DIO line - to trigger, I should connect it to one of the PFI lines and I cannot acquire from a PFI line. Is there any way around this? One other reason why I do not want to connect that signal to the PFI line is that the PFI line is pulling it low when that signal actually has a pull - up. Is there any way to make a PFI line High Z?

Thanks,

Priyatham.

[Ryan_M]

Priyatham,

I'll start with your second question.  Yes you can explicitly tristate your PFI using the DAQmx connect vis.  The channel electronics of the 6551 have a 10k or 50k ohm pull down depending on how old your device is.  If your pull up is stronger than that then you should have no trouble tristating the PFI to a high level.

In response to your larger scenario, the only triggering options available on a signal input to a data line is the pattern match triggers which are only available for acquisition.  Assuming you can't split the chip select line, you may be able to achieve this if you setup a pattern match reference trigger, you can fetch your data relative to the first sample (basically ignorning the reference trigger) and reexport your reference trigger to an unused PFI.  You can then use that PFI as a start trigger for your generation.  The downside is that the memory is treated as a circular buffer with a certain number of pretrigger and post trigger samples.  If you capture more data before the reference trigger than you have configured pretrigger samples, you run the risk of over writting data.  To prevent this you must continually fetch data from the hardware (streaming examples) or make sure that the pre and post trigger counts make sense for your waveform size.  This will probably take some trial and error testing.

In summary, the 6551 wasn't designed to trigger generation from an acquired data signal.  It can be done, but it has many caveats and conditions.  The piece of hardware Charles is describing is ideally suited for these sort of applications.  Since it is LabVIEW FPGA based, you can implement any type of triggering you want.  Additionally, the 6581 has the same pinout as the 6551 so you can migrate very easily between platforms.

[Priyatham]

Hi Ryan
 
Thankyou very much for the reply, that was a great help. Now I got one more question:
 
I have been trying to use 6551 as a SPI Slave. Here's what I have been doing:

I have a Dynamic Generation engine and a Dynamic Acquisition Engine in the SPI Slave State. I'm triggering both the Acquisition and the Generation Engine on the falling edge of the CSN, then Im generating the SPI Slave data on MISO bit by bit using a sample clock that is 6x my SPI Master clock. I need to send out data on 17-24 clocks of my SPI clock after the CSN goes Low. So I had assumed once I use the CSN as my Gen. trigger I can send out data on the 102 - 144 (17x6 - 24x6) clocks of my sample clock. But its not working out that way, What I see is a delay of my data on MISO after the CSN goes low. So I was wondering if there's some sort of software delay in between the Generation trigger and the Generation Data. I dont care if there's a delay which is deterministic and the same every time, but I probably cannot deal with varying delays.
 
I'd greatly appreciate any help on this. 

Thanks,

Priyatham. 

[Priyatham]

Answer to my previous question:

There is a deterministic hardware delay between the generation trigger and the generation data.  This delay is 32 cycles + 160ns and is always the case.  It depends on your clocking rate of course, so if you have a 100 MHz clock then it is 320ns + 160ns.  If your clock is slow this delay will seem large.  To reduce this delay you can speed up your clock and over sample your data.  This information is in the specifications document.

Thanks Raajit Lall, for the answer.

Now I have one more question:

I have two states – SPI Master and SPI Slave. In my SPI Master state I configure the registers and write an instruction config done. As soon as my DUT detects this instruction it takes over as the SPI Master and now I have to acquire the signals it sends out as an SPI Slave. But as I have these two configurations in two different states, I think its taking some time for the state transition from SPI Master to SPI Slave - as a result I’m not able to acquire the very first signal my DUT sends out. I’m rather acquiring signals after a period of time. Is there any way to avoid this state transition delay? Is there a better coding practice for this type of situations? Would merging the two states help? Merging these two states might be messy in my case, but I will give it a try if that’s the only option.