The PCI-6111 board has the same digital capabilities as our E-series boards. Depending on what programming language you are using, there should be some digital IO shipping examples.
Another source for code examples is our DevExchange: http://zone.ni.com/zone/jsp/zone.jsp
Thanks for your replay. I need to acquire digital data form 3 lines : Line 1: CLK -1 Mbps Line 2: DATA - format = 1 sample = [16bit I][16bit Q][8 bit ACC][10 bit 0] = 20 ksamples/sec = 1 Mbps Line 3: SYNC - 20 kbps I have in my position PCI 6111E and PCI 6534 and Labview I would like to use the CLK signal as trigger at down, and acuire the data first to data file and after dynamicly to MATLAB.
1. Which PCI is more suitable for this task? 2. Can I activate Labview VI as server from MATLAB? 3. I just started with Labview and used "Buffered Pattern Input Digital Waveform" example, but i manage to acquire only 2 lines with PCI 6534?
1) Since you are perfroming the high speed digital IO, I would suggest that you use the 6534 digital IO card.
2) I'm not sure about the VI server with Matlab. From what I've seen, people typically build their LabVIEW programs into C dlls that they can call from Matlab.
3) Depending on the version of LabVIEW that you are running, you should have some 6534 specific examples. I'm not exactly sure what the problem is. I would need a lot more information before I can comment on what is going on with that.
I have decided to use PCI 6534 and BNC-2110 of NI. I am also using LABVIEW example program "Buffered_Pattern_Input_Digital_WaveForm_Graph_653X.vi" as first try. (I also added "File.." component to save the acquired signals.) I can see all 3 digital lines data when they are connected to port 0, DIO0~7 lines, and program configured to internal clock.
I would like to use my clk line as trigger to the other 2 lines. I connected clk line to PFI0/TRIG1 PIN, and set the program to external but didn't see any response.
1. Is that possible connection? 2. How can I acquire the data and sync lines by using clk as trigger (falling Edge) in the following configuration?
I'm not exactly sure what you are trying to do. Could you send me the modified VI that you are currently using and I can take a look at it. Also, maybe more description of what you are trying to do.
You have a clock signal on line 1 and you what lines 2 & 3 to be triggered on the clock. This means that you want to latch the data on lines 2 and 3 on the rising edge of the clock signal on line 1, correct?
I would like to use my CLK line as external trigger to the 2 other lines, (Data,SYNC). I would like to configure the trigger to falling edge.
I would also like to read/save the triggered Data and SYNC information to a file.
At the current state I manage to see all 3 lines on the graph display, but i can not read them to a file properly. When i open the file i get values like 32, 64 ... and not "0" / "1".
Your code is saving the data to a file in the unsigned 8 bit integer datatype. You digital read is returning a integer interpretation of an 8 bit binary number. For example, if your digital pattern was 0000 1001 it would be saved as 2^4 + 2^1 = 17, so your file would have an "8" saved. So from your integers you should be able to know what the digital pattern was. If your file has the intergar value 64 saved, it would correspond to 0010 0000.