rising and falling edge in 6541

[TomasMotos]

Hello

I intend to use the PXI-6541 to sample a 4-bits digital signal. That signal comes with an associated 19 MHz clock, which is within the spec of that instrument. However, my problem comes from the fact that the signal should be sampled during both the negative and positive edge of that clock (i.e. the actual signal rate is 38 MHz).

While browsing the documentation, I find that the niHSDIO_ConfigureDataPosition just allows either positive or negative rising edges for data capture:

ViStatus niHSDIO_ConfigureDataPosition (ViSession vi, ViConstString channelList, ViInt32 position);

position:
NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE (18)—The device samples or generates data on the rising edge of the Sample clock.
NIHSDIO_VAL_SAMPLE_CLOCK_FALLING_EDGE (19)—The device samples or generates data on the falling edge of the Sample clock.
NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE (20)—The device samples or generates data with delay from rising edge of the Sample clock

Is it possible to program the intrument to sample at both edges (or'ing the constants, for instance) or is this operation not permitted in this device? In this case, is there any work around I could implement to sample that signal?

Tomas

[Ryan_M]

Tomas,

The 654x and 655x do not support what you are describing.  The 656x (LVDS device) supports a mode called DDR in which data may be sampled on both the rising edge and falling edge of a clock.  The 654x only supports SDR mode in which the data may be sampled on the rising, falling, or a delay from the rising edge of the clock.  However, you can have different channels sample at different positions.  For example, if you can send the same data to channel 0 and channel 1 then you may have channel 0 sample on the rising edge and channel 1 sample on the falling edge.  You could then perform some software post processing to recombine the data.

[TomasMotos]

Thanks for the prompt answer. It is not the best of the solution, but something that might work.

Let's say now that I configure signals A B C and D into channels 0 - 3 to be sampled on the rising edge and the same signals (let's call tehm A' B' C' D' although they are the same signals at source) into channels 4-7 to be sampled on the falling edge. How would my vector look like after a read command? Would each sampling event produce an entry into the resulting samples vector (in this fashion) ?

0    1   2    3     4    5     6    7
-----------------------------------------
A0 B0 C0 D0 - X    X    X    X      <- positive edge
A0 B0 C0 D0 - A0' B0' C0' D0'   <- negative edge
A1 B1 C1 D1 - A0' B0' C0' D0'   <- positive edge
A1 B1 C1 D1 - A1' B1' C1' D1'   <- negative edge
A2 B2 C2 D2 - A1' B1' C1' D1'   <- positive edge
...

i.e. in even samples new data would be present on channels 0-3 and in odd samples on 4-7?


Thanks in advance
Tomas

[Ryan_M]

Tomas,

In your example, the data stored into memory would be rows 1 and 2 as a single sample, then 3 and 4 as a single sample, etc.  Pardon my artistic abilities but I drew up a quick timing diagram to illustrate.

This illustration is of a quick test I ran here at my desk.  In my test, I have a device (6542) generating data on channels 0-7.  I have channels 0-3 generate on the rising edge of the clock (TCO is illustrated) and channels 4-7 generate on the falling edge of the clock.  In this fashion, I can simulate your DDR source where I have data being generated on the rising edge and falling edge of the clock.  Also, I generate a data active event on the rising edge of the clock to be used as a start trigger.

I then connect the exported sample clock from my generation into STROBE of my acquisition, and channels 0-7 to channels 16-23.  I configure channels 16-19 to acquire the data on the rising edge of the clock and channels 20 to 23 to acquire on the falling edge of the clock.  Also, I setup a rising edge start trigger to be sampled on the rising edge of the clock (driven by my data active event).

The drawing shows the timing relationship between the exported signals and the sample positions.  In this case, my first sample begins at the start trigger and includes the first rising edge AND the first falling edge of the clock after that start trigger so my first sample would be AA.  You would then need to have software split that single sample into two samples, A and A.

Does that make sense?

Message Edited by Ryan M on 11-17-2006 10:13 AM