First of all Great use of State machines, you code was well organized for the most part, which is refreshing.
The best way to pass data between two loops is using a producer consumer architecture with cues.
As for your TDMS timing, you can reduce the longest data path through your read loop (combinatorial path). Count the greatest number of consecutively wired nodes, and make it smaller. You have a bunch of shared variable access that has to happen after the TDMS read but before the next loop iteration. One such method for improving speed here is pipelineing, this is most commonly used on the FPGA itself, but the reasoning for the real time host is the same.
Let me know if I need to elaborate on ay of these ideas.
